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Support RHS of ==? or !=? as a indexed element into parameter array #821

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veripoolbot opened this issue Sep 14, 2014 · 1 comment
Open

Support RHS of ==? or !=? as a indexed element into parameter array #821

veripoolbot opened this issue Sep 14, 2014 · 1 comment

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@veripoolbot veripoolbot commented Sep 14, 2014


Author Name: Iztok Jeras (@jeras)
Original Redmine Issue: 821 from https://www.veripool.org


I wrote an RISC-V disassembler in SystemVerilog.

https://github.com/jeras/riscv_asm_sv

Verilator is actually not the primary target, but it would be useful to have it supported. The API component is a function accepting as input a 32bit instruction and providing as output a disassembled string. Instructions are listed in a parameter, which is an array of structures. The given binary code is compared (wildcard equivalence) against elements of the parameter in a for loop. Verilator complains that an indexed element of the array is not a constant. This is kind of synthesizable code, but the purpose is obviously for it to be part of a bench. Since this is probably not trivial to fix, I do not expect a solution soon.

Interestingly the ==? operator does not work correctly in ncsim, while it works well in ModelSim. I was surprised to see it properly implemented in Verilator.

Related to the same example is the support for the $sformatf and related system tasks/functions.

$ verilator --lint-only riscv_asm.sv
%Error: riscv_asm.sv:46: Unsupported tristate construct: INITARRAY
%Error: riscv_asm.sv:240: Unsupported: RHS of ==? or !=? must be constant to be synthesizable

Regards,
Iztok Jeras

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@veripoolbot veripoolbot commented Sep 21, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-09-21T12:53:36Z


Looked at this a bit and it is not easy because Verilator removes all tristates (wildcards in this case) at compile time.

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