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Support RHS of ==? or !=? as a indexed element into parameter array #821
I wrote an RISC-V disassembler in SystemVerilog.
Verilator is actually not the primary target, but it would be useful to have it supported. The API component is a function accepting as input a 32bit instruction and providing as output a disassembled string. Instructions are listed in a parameter, which is an array of structures. The given binary code is compared (wildcard equivalence) against elements of the parameter in a for loop. Verilator complains that an indexed element of the array is not a constant. This is kind of synthesizable code, but the purpose is obviously for it to be part of a bench. Since this is probably not trivial to fix, I do not expect a solution soon.
Interestingly the ==? operator does not work correctly in ncsim, while it works well in ModelSim. I was surprised to see it properly implemented in Verilator.
Related to the same example is the support for the $sformatf and related system tasks/functions.
$ verilator --lint-only riscv_asm.sv