Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

/*verilator tracing_off*/ causes compile errors #826

Closed
veripoolbot opened this issue Sep 30, 2014 · 11 comments
Closed

/*verilator tracing_off*/ causes compile errors #826

veripoolbot opened this issue Sep 30, 2014 · 11 comments

Comments

@veripoolbot
Copy link

@veripoolbot veripoolbot commented Sep 30, 2014


Author Name: Lane Brooks
Original Redmine Issue: 826 from https://www.veripool.org
Original Date: 2014-09-30


We are embedding a Xilinx microblaze processor into an FPGA. I want tracing for it and all its dependencies disabled while leaving tracing for the complete rest of the design enabled. If I wrap /verilator tracing_off/ around the instantiation of the processor and that seems to have no effect as all the microprocessor signals and its submodules still come through. Instead I add it as the first and last line of the microprocessor module, and it fails to verilate with %Warning-MULTIDRIVEN messages like the following:

%Warning-MULTIDRIVEN: ../../../lib/xilinx/RAMB16BWER.v:147: Signal has multiple driving blocks: MCS.mcs_0.U0/lmb_bram_I/RAM_Inst/Using_B16_S2.The_BRAMs[15].RAMB16_S2_1.mem

Am I misusing the /verilator tracing_off/ directive? Is there a way to turn off tracing down one branch of the hierarchy?

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Sep 30, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-09-30T20:38:18Z


At present verilator tracing_off turns off tracing around any signals/variables that are encountered. If there's a cell it doesn't mean don't trace within that cell - to do that you would need the pragma above any module statements and the ones below that module as you noticed.

I do not object to changing this behavior, the pragma results in setting a flag attached to each FileLine - so where the trace routines process Cells just test it before iterating, I'd be glad to take that patch back.

Tracing disables some optimizations, so that is what is almost certainly causing the error, though I'm a bit surprised that a MULTIDRIVEN was the result so perhaps it's more an indirect effect.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Oct 3, 2014


Original Redmine Comment
Author Name: Dennis Muhlestein
Original Date: 2014-10-03T03:31:49Z


So from your comment do I understand correctly that you can't disable an entire subtree easily?

I've tried the tracing commands lane mentioned and also with verilator config in a config file

 `verilator_config
 tracing_off -file "<path to microblaze.v>"
 tracing_off -file "<path to xilinx libs/*.v"

Result is the same though, 3G+ vcd files and it doesn't appear the tracing is turned off.

I suppose we could modify our dump call to take a parameter for the number of levels but we need the traces in other modules that are leveled deeper than the micro controller.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Oct 9, 2014


Original Redmine Comment
Author Name: Lane Brooks
Original Date: 2014-10-09T15:17:44Z


Wilson,

Is there any other way to disable tracing only on a certain branch of the hierarchy?

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Oct 10, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-10-10T13:23:44Z


At present there is not another way to disable the hierarchy, but I think the patch to disable a cell if trace_off is currently off for that cell would be quite easy.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Oct 10, 2014


Original Redmine Comment
Author Name: Dennis Muhlestein
Original Date: 2014-10-10T21:45:03Z


I'm quite new to the verilator sources but if you pointed me in the right direction to look I could probably add that support.

It seems to me it should work like this:

 wire x; // trace file would have data for x but nothing for any of the signals or additional modules used in y.
 // verilator tracing_off
 somemodule y (.trace_signal(x));
 // verilator tracing_on
@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Oct 14, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-10-14T16:07:34Z


First, create/modify a test_regress/t test that disables tracing on a cell using the trace_off/trace_on markers. Run it and it should fail since you haven't implemented it.

In verilog.y you'll see nodep->trace is set on a AstVar object. Add a new similar trace method to AstCell, and set that similarly where cells are created in verilog.y.

Then in L3LinkDot which recurses through cells, in the AstVar visitor, if m_cellp->trace() (which you saved state for in verilog.y) is clear, clear that variable's trace attribute.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Oct 23, 2014


Original Redmine Comment
Author Name: Dennis Muhlestein
Original Date: 2014-10-23T16:20:51Z


Ok so it looks like the context of the cell visitor and the var visitor don't overlap. Maybe I'm looking in the wrong spot.

V3LinkDot.cpp , only class with m_cellp is LinkDotResolveVisitor

That class has

 virtual void visit(AstCell* nodep, AstNUser*); 
 // and
 virtual void visit(AstVar* nodep, AstNUser*);

Amongst the rest.

I placed a couple trace statements in those methods and found that visit cell exits before any visit var calls are made. in visit cell m_cellp is set back to NULL.

So anyway, I was able to modify the lexer easily enough and set the debug flag on the module but I'm not quite seeing how to get from cell to variable.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Oct 24, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-10-24T00:31:00Z


Can you point to your code, including a self-test?

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Nov 8, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-11-08T19:16:15Z


Pushed to git the changes to make trace_off apply to child cells.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Nov 8, 2014


Original Redmine Comment
Author Name: Dennis Muhlestein
Original Date: 2014-11-08T19:19:01Z


Awesome I'll test the changes out.

Sorry I hadn't had a chance to respond w/ my test case or start of the code I'd worked on. Been very busy with a few issues that are bigger on the totem pole.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Nov 15, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-11-15T13:46:13Z


In 3.866.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
1 participant
You can’t perform that action at this time.