Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

How to access SV enums via /*verilator public*/ #833

Closed
veripoolbot opened this issue Oct 27, 2014 · 3 comments
Closed

How to access SV enums via /*verilator public*/ #833

veripoolbot opened this issue Oct 27, 2014 · 3 comments

Comments

@veripoolbot
Copy link

@veripoolbot veripoolbot commented Oct 27, 2014


Author Name: Jonathon Donaldson
Original Redmine Issue: 833 from https://www.veripool.org
Original Date: 2014-10-27
Original Assignee: Wilson Snyder (@wsnyder)


I'm not sure if it's something that I'm doing wrong or if it's simply just not supported yet, but I'm wondering how/if I can access the enums in my SV code from within my C++ code. With basic SV parameters using /verilator public/ works really well. But if I try to use it with enums I keep getting a verilator syntax error. For example:

  typedef enum logic [7:0] {
     KE = "0",
     KV = "K",
     SE = "1",
     SV = "S"
  } T_Usr_Rsp /*verilator public*/;

The above results in:

%Error: my_package.sv:124: syntax error, unexpected /*verilator public*/, expecting ';'

If it's not currently supported I wonder if verilator could simply treat the SV enums as if each enumeration was simply a set of independent parameters (maybe that way verilator could leverage what's already supported)?

Right now I have to copy each SV enum code block into my C++ code somewhere and manual translate it to C++ syntax. Not a huge deal, but it is quite a bit of code duplication that would be great to get rid of.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Oct 27, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-10-27T16:34:39Z


Enums are presently flattened and not put into the C code.

Often enums come from CSRs or such, and a company has some flow to autogenerate such enums for both C and Verilog, so verilator doesn't have to translate them.

However if you want to add support for this please feel free. I don't think they should become parameters but real enumerations. They will need to be in a separate class as in Verilog they are separate namespaces (e.g. EnumName::FOO and AnotherEnumName::FOO).

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Nov 7, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-11-07T12:51:08Z


Public typedefs now in git - please see the manual.

@veripoolbot veripoolbot closed this Nov 7, 2014
@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Nov 8, 2014


Original Redmine Comment
Author Name: Jonathon Donaldson
Original Date: 2014-11-08T00:04:34Z


This is totally awesome! Can't thank you enough for this. Works great too! This will save tons of code duplication.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
2 participants
You can’t perform that action at this time.