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Verilator doesn't trace code below the primitive definition within same file #837

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veripoolbot opened this issue Nov 4, 2014 · 3 comments

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@veripoolbot veripoolbot commented Nov 4, 2014


Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 837 from https://www.veripool.org
Original Date: 2014-11-03


For the following code, Verilator will fail to trace the module @sub_t@

module t
  (
    clk
    );

    input clk;
    integer    cyc; initial cyc = 0;

    reg a;
    reg b;
    reg z;
    sub_t sub_t_i (z, a, b);

    always @ (posedge clk) begin
       cyc <= cyc + 1;
       a <= cyc[0];
       b <= cyc[1];

       if (cyc > 10) begin
           $write("*-* All Finished *-*\n");
           $finish;
       end
    end
endmodule

primitive CINV (a, b);
output b;
input a;
assign b = ~a;
endprimitive

module sub_t (z, x, y);
input x, y;
output z;

assign z = x & y;
endmodule

The XML file says the signals in @sub_t@ are all trace_off.

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@veripoolbot veripoolbot commented Nov 4, 2014


Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2014-11-04T08:42:54Z


Both a test case and fix are push to my github. http://github.com/jiexu/verilator.git -b trace_primitive

The reason is because Verilator will start a @tracing_on(false)@ when @primitive@ occurs in the code. And the @tracing_on(false)@ will last to the end of that file.

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@veripoolbot veripoolbot commented Nov 4, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-11-04T12:50:31Z


Thanks esp for a test. I fixed it slightly differently looking ahead to when/if primitives are handled better.

Fixed in git towards 3.865.

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@veripoolbot veripoolbot commented Nov 15, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-11-15T13:46:33Z


In 3.866.

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