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Trouble mixing older Verilog port syntax with SystemVerilog interfaces #868
I am receiving the following error:
syntax error, unexpected '.', expecting IDENTIFIER
I inherited a number of Verilog files that I need to convert to SystemC. For some reason the port list is in the old Verilog format but then uses new SytemVerilog interfaces. I have produced a very stripped down example below that mimics this and I compiled it with unused, undriven warnings suppressed:
If the `define is uncommented, the error that I specified before is generated.
Original Redmine Comment
Thanks for the test case. Surprisingly it looks like Verilog-Perl's parser that should handle almost everything gets this wrong too, so verilator inherited it.
Fixed in Verilog-Perl git towards 3.409
Fixed in verilator git towards 3.869.