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Trouble mixing older Verilog port syntax with SystemVerilog interfaces #868

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veripoolbot opened this issue Jan 7, 2015 · 3 comments
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@veripoolbot veripoolbot commented Jan 7, 2015


Author Name: Kevin Thompson
Original Redmine Issue: 868 from https://www.veripool.org
Original Date: 2015-01-07
Original Assignee: Wilson Snyder (@wsnyder)


I am receiving the following error:

syntax error, unexpected '.', expecting IDENTIFIER

I inherited a number of Verilog files that I need to convert to SystemC. For some reason the port list is in the old Verilog format but then uses new SytemVerilog interfaces. I have produced a very stripped down example below that mimics this and I compiled it with unused, undriven warnings suppressed:

//`define OLD_PORT_LISTING 1

interface addr_if();
    
    logic aready;
    logic aid;
    
    modport master(input aready, output aid);

    modport slave(output aready, input aid);

endinterface


`ifdef OLD_PORT_LISTING
module mc_test(dclk,
                axi0_if);

    input dclk;
    addr_if.slave axi0_if;

endmodule

`else

module mc_test(input dclk,
	       addr_if.slave axi0_if);

endmodule

`endif

module mc_top();

    logic dclk;

    addr_if addr_if_dut();
  
    mc_test test_module(dclk, addr_if_dut.slave);
    
endmodule

If the `define is uncommented, the error that I specified before is generated.

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@veripoolbot veripoolbot commented Jan 17, 2015


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-01-17T20:38:08Z


Thanks for the test case. Surprisingly it looks like Verilog-Perl's parser that should handle almost everything gets this wrong too, so verilator inherited it.

Fixed in Verilog-Perl git towards 3.409

Fixed in verilator git towards 3.869.

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@veripoolbot veripoolbot commented Jan 20, 2015


Original Redmine Comment
Author Name: Kevin Thompson
Original Date: 2015-01-20T22:18:36Z


Thank you for fixing this issue.

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@veripoolbot veripoolbot commented Feb 13, 2015


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-02-13T01:41:12Z


In 3.870.

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