Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Verilator segfaults in V3Gate warning #911

Closed
veripoolbot opened this issue Apr 24, 2015 · 5 comments
Closed

Verilator segfaults in V3Gate warning #911

veripoolbot opened this issue Apr 24, 2015 · 5 comments

Comments

@veripoolbot
Copy link

@veripoolbot veripoolbot commented Apr 24, 2015


Author Name: Eivind Liland
Original Redmine Issue: 911 from https://www.veripool.org
Original Date: 2015-04-24
Original Assignee: Jie Xu (@jiexu)


It happens unpredictably on various modules and with different versions of verilator (including the newest one). It varies from computer to computer and from session to session whether the problem occurs or not. (I would suspect that verilator is reading uninitialized memory?)

The problem occurs with different messages:

  • Segmentation fault (core dumped)
  • %Error: Verilator internal fault, sorry. Consider trying --debug --gdbbt
  • Killed! (and something more - not able to reproduce this at the moment)

We've tried to create a reduced version of our sources, but haven't been successful so far because the error is hard to reproduce in a reliable way.

Attaching debug information

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Apr 24, 2015


Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2015-04-24T12:03:06Z


Hi, looked into both of your debug info files. The errors happen at in V3Gate.cpp where it tries to generate SYNCASYNCNET warning.

To me the reason it happens is that the node it try to find is already deleted in a earlier stage. It would nice to share your altera_avalon_mm_clock_crossing_bridge.v or at least the part with warnings.

Also when you have the callback from the debugger, go back to the frame of GateVisitor::warnSignals() and check which signal is the problem. You can find a GDB script file verilator source src/.gdbinit where some function are defined to check the node. But I don't know if you can do something similar in LLDB.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Apr 24, 2015


Original Redmine Comment
Author Name: Sebastian Dressler
Original Date: 2015-04-24T12:55:45Z


Hi,

We do not get a segfault, when using the verilator_bin_dbg, there we retrieve proper warnings and are able to detect the signal causing this. However, when using plain verilator_bin it segfaults. I was able to do a detailed traceback after compiling with ```-g -O0


Cheers,
Sebastian
@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Apr 24, 2015


Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2015-04-24T13:32:24Z


Seems to me this is a clear error which should be reproducible on every run unless there are some different optimization options when calling Verilator.

If my assumptions are correct, you can try the patch:

diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp
index e933ae4..039e30d 100644
--- a/src/V3Gate.cpp
+++ b/src/V3Gate.cpp
@@ -360,6 +360,8 @@ private:
      // VISITORS
      virtual void visit(AstNetlist* nodep, AstNUser*) {
         nodep->iterateChildren(*this);
+       // Warn
+       warnSignals();
         //if (debug()>6) m_graph.dump();
         if (debug()>6) m_graph.dumpDotFilePrefixed("gate_pre");
         m_graph.removeRedundantEdgesSum(&V3GraphEdge::followAlwaysTrue);
@@ -373,8 +375,6 @@ private:
         // Remove redundant logic
         if (v3Global.opt.oDedupe()) dedupe();
         if (v3Global.opt.oAssemble()) mergeAssigns();
-       // Warn
-       warnSignals();
         consumedMark();
         m_graph.dumpDotFilePrefixed("gate_opt");
         // Rewrite assignments


Basically I move the warning part before the optimizations in V3Gate where some nodes could be optimized out.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Apr 27, 2015


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-04-27T10:47:38Z


Thanks for patching, makes sense. Fixed in git towards 3.873.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Jun 6, 2015


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-06-06T18:03:48Z


In 3.874.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
1 participant
You can’t perform that action at this time.