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WIdth bug related to size casting #925

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veripoolbot opened this issue Jun 1, 2015 · 6 comments
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WIdth bug related to size casting #925

veripoolbot opened this issue Jun 1, 2015 · 6 comments
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@veripoolbot veripoolbot commented Jun 1, 2015


Author Name: Jonathon Donaldson
Original Redmine Issue: 925 from https://www.veripool.org
Original Date: 2015-06-01
Original Assignee: Wilson Snyder (@wsnyder)


Verilator calculates the incorrect result for the following equation:

localparam [6:0] RESULT = 7'((6*9+92)%96);

Verilator calculates a value of 18. However, the correct result is 50.

After a bit of investigation I determined that the issue is that verilator is truncating the internal (69+92) quantity to 7 bits. However, the entire ((69+92)%96) quantity should be calculated as a 32-bit expression and only truncated to 7 bits just before the assignment.

Altera and Xilinx synthesis tools both calculate the result as 50. Modelsim also calculates the result as 50. I believe that you (Wilson) use VCS - it would be interesting to know what result it calculates.

I have attached an example in test regress format.

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@veripoolbot veripoolbot commented Jun 1, 2015


Original Redmine Comment
Author Name: Jonathon Donaldson
Original Date: 2015-06-01T06:40:44Z


I found another example of this bug that seems to be very similar. I'm not sure if it's the exact same issue or not so I decided just to append to this bug report. I have attached the example in test regress format.

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@veripoolbot veripoolbot commented Jun 4, 2015


Original Redmine Comment
Author Name: Jonathon Donaldson
Original Date: 2015-06-04T01:58:17Z


Just FYI, I did a quick test with t_math_arith2 in Aldec Active-HDL earlier today and it also got the expected answer. I didn't have time to test t_math_arith3 and I don't have access to the simulator anymore, but I imagine it would also get the same expected result (obviously I can't say for certain though).

I'm still interested in what VCS has to say as well. :) Wish I had access to all the simulator/synthesis tools to see if there was a general consensus on a particular result. Seems that way from the 4 that I've tested so far...but there's so many out there... If there is a mainstream simulator/synthesis tool that generates a different result it would start to make me think there is some ambiguity in the standard.

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@veripoolbot veripoolbot commented Jun 4, 2015


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-06-04T02:59:51Z


I confirmed this in VCS, and fixed it, however it breaks other tests because casts don't seem to expand quite as simply as the spec suggests. Stay tuned.

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@veripoolbot veripoolbot commented Jun 4, 2015


Original Redmine Comment
Author Name: Jonathon Donaldson
Original Date: 2015-06-04T06:35:01Z


Very interesting stuff. Thanks for the update. I'm eager to see what you find out.

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@veripoolbot veripoolbot commented Jun 6, 2015


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-06-06T17:47:17Z


Fixed in git towards 3.873.

The IEEE spec doesn't say that casts should be treated like assignments to a variable of the appropriate cast size, followed by appropriate extension/truncation, but that's what seems to need to happen.

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@veripoolbot veripoolbot commented Jun 6, 2015


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-06-06T18:05:11Z


In 3.874.

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