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$signed ignored under generate block #999
A PicoRV32 user reported problems with simulating the PicoRV32 CPU with Verilator. So I investigated and found the following bug in Verilator. Sorry for not positing a minimalist test case. I've tried to create one from scratch, but was unable to reproduce the problem this way.
Here is the problem: http://i.imgur.com/evkRLNx.png
alu_lts clearly should be high when reg_op1 is -1 and reg_op2 is 0. But it seems like Verilator incorrectly merges the alu_lts and alu_ltu signal.
Using current git head of verilator (4e4bc7b):
Interestingly, in the larger test bench that includes PicoRV32, the signals alu_lts and alu_ltu are not merged, but are still assigned the same expressions. Looking at the generated c++ code:
In this case, manually changing the assignment for alu_lts fixes the problem and the testbench runs successfully:
Original Redmine Comment
I have now successfully created a minimal test case:
This produces the following (incorrect) code for alu_lts and alu_ltu:
The generated code is correct when the 'generate if' and 'end generate' lines are removed:
(This is with "verilator -Wno-fatal --trace --cc test.v".)