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Support $bits on typedef of a union
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4521
opened Sep 26, 2023 by
polyee13
Can't generate correct tex name
area: documentation
Issue involves documentation
status: asked reporter
Bug is waiting for reporter to answer a question
#4519
opened Sep 26, 2023 by
cheungxi
forceable signal can not be forced when --coverage-toggle option is activated
area: coverage
Issue involves coverage generation
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4514
opened Sep 21, 2023 by
fredrequin
Add option to write output of executable to log file
area: usability
Issue involves general usability
type: feature-non-IEEE
Request to add new feature, outside IEEE 1800
#4505
opened Sep 18, 2023 by
tudortimi
Add standard waivers?
area: lint
Issue involves SystemVerilog lint checking
status: discussion
Issue is waiting for discussions to resolve
#4501
opened Sep 18, 2023 by
wsnyder
Fix uvm_sequencer wrong reference type
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4497
opened Sep 16, 2023 by
wsnyder
Support UVM delayed assignment inside public function/task
area: scheduling
Issue involves scheduling/ordering of events
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4496
opened Sep 16, 2023 by
wsnyder
Support UVM waiting on local event variables
area: scheduling
Issue involves scheduling/ordering of events
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4495
opened Sep 16, 2023 by
wsnyder
Support UVM #0 ZERODLY
area: scheduling
Issue involves scheduling/ordering of events
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4494
opened Sep 16, 2023 by
wsnyder
Fix variable not declared with fork local
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4471
opened Sep 10, 2023 by
wsnyder
Fix UVM assignment of event data types
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4468
opened Sep 9, 2023 by
wsnyder
Support Issue involves scheduling/ordering of events
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-IEEE
Request to add new feature, described in IEEE 1800
wait fork
area: scheduling
#4465
opened Sep 9, 2023 by
wsnyder
wait(event) causes compile error rather than parse error
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4457
opened Sep 6, 2023 by
jwoutersymatra
Systemverilog repeat loop (counter) lifetime error
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4451
opened Aug 31, 2023 by
jwoutersymatra
Fix function_fork_valid regression with unknown type
area: scheduling
Issue involves scheduling/ordering of events
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4449
opened Aug 30, 2023 by
wsnyder
Fix x-assign unique when index out-of-range of an unpacked struct array
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4445
opened Aug 28, 2023 by
tastynoob
Support sequence
status: asked reporter
Bug is waiting for reporter to answer a question
type: feature-IEEE
Request to add new feature, described in IEEE 1800
#4425
opened Aug 17, 2023 by
Divya2030
--x-initial-edge triggers unwanted edge on first model eval
area: scheduling
Issue involves scheduling/ordering of events
status: asked reporter
Bug is waiting for reporter to answer a question
#4424
opened Aug 16, 2023 by
Dolu1990
Support --lib-create option with --timing
area: scheduling
Issue involves scheduling/ordering of events
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
type: feature-non-IEEE
Request to add new feature, outside IEEE 1800
#4410
opened Aug 9, 2023 by
TarasSmarkutskyi
$monitor prints intermediate values during simulation deltas
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
effort: hours
Expect this issue to require roughly hours of invested effort to resolve
good first issue
Good for newcomers
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4400
opened Jul 31, 2023 by
amanvm
Unlinked when getting bit width of type defined in parameterized class
area: elaboration
Issue involves elaboration phase
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4391
opened Jul 27, 2023 by
em2machine
Fix lint check for %m with assoc array
area: lint
Issue involves SystemVerilog lint checking
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4376
opened Jul 19, 2023 by
solomatnikov
BLKANDBLK error on SV queue
area: elaboration
Issue involves elaboration phase
effort: days
Expect this issue to require roughly days of invested effort to resolve
good first issue
Good for newcomers
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4373
opened Jul 19, 2023 by
shareefj
$strobe and $monitor fail inside of task and with task output as argument
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4369
opened Jul 17, 2023 by
mczyz-antmicro
Fix handling of clocks embedded in SV structs
area: scheduling
Issue involves scheduling/ordering of events
status: ready
Issue is ready for someone to fix; then goes to 'status: assigned'
#4363
opened Jul 13, 2023 by
em2machine
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