From d0aefee149388ce78e08b649d5c41158797fefbc Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Sat, 19 Jun 2021 18:50:57 -0700 Subject: [PATCH 1/4] Adding test case --- test_regress/t/t_source_sync.pl | 20 ++++++++++++++++++++ test_regress/t/t_source_sync.v | 24 ++++++++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100755 test_regress/t/t_source_sync.pl create mode 100644 test_regress/t/t_source_sync.v diff --git a/test_regress/t/t_source_sync.pl b/test_regress/t/t_source_sync.pl new file mode 100755 index 0000000000..e2b4279f9e --- /dev/null +++ b/test_regress/t/t_source_sync.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +compile( + ); + +execute( + ); + +ok(1); +1; diff --git a/test_regress/t/t_source_sync.v b/test_regress/t/t_source_sync.v new file mode 100644 index 0000000000..4cf11f0c37 --- /dev/null +++ b/test_regress/t/t_source_sync.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Use this file as a template for submitting bugs, etc. +// This module takes a single clock input, and should either +// $write("*-* All Finished *-*\n"); +// $finish; +// on success, or $stop. +// +// The code as shown applies a random vector to the Test +// module, then calculates a CRC on the Test module's outputs. +// +// **If you do not wish for your code to be released to the public +// please note it here, otherwise:** +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Dan Petrisko. +// SPDX-License-Identifier: CC0-1.0 + +typedef struct packed { + logic clk /*verilator clocker*/; + logic data; +} ss_s; + +endmodule From 100aeb119b06e0662e9cca946ea8f7c9f9d57480 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Tue, 29 Jun 2021 17:48:17 -0700 Subject: [PATCH 2/4] Updating test to failure --- test_regress/t/t_source_sync.out | 7 +++++++ test_regress/t/t_source_sync.pl | 7 +++---- 2 files changed, 10 insertions(+), 4 deletions(-) create mode 100644 test_regress/t/t_source_sync.out diff --git a/test_regress/t/t_source_sync.out b/test_regress/t/t_source_sync.out new file mode 100644 index 0000000000..257e767bd9 --- /dev/null +++ b/test_regress/t/t_source_sync.out @@ -0,0 +1,7 @@ +%Error: t/t_source_sync.v:20:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';' + 20 | logic clk /*verilator clocker*/ ; + | ^~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_source_sync.v:22:1: syntax error, unexpected '}' + 22 | } ss_s; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_source_sync.pl b/test_regress/t/t_source_sync.pl index e2b4279f9e..f34ef865a9 100755 --- a/test_regress/t/t_source_sync.pl +++ b/test_regress/t/t_source_sync.pl @@ -8,12 +8,11 @@ # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(linter => 1); +scenarios(vlt => 1); compile( - ); - -execute( + fails => 1, + expect_filename => $Self->{golden_filename}, ); ok(1); From 80407f145b77e04758b8f1dd3859f38ad24ca257 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Tue, 29 Jun 2021 17:48:52 -0700 Subject: [PATCH 3/4] Update test_regress/t/t_source_sync.v Co-authored-by: Wilson Snyder --- test_regress/t/t_source_sync.v | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/test_regress/t/t_source_sync.v b/test_regress/t/t_source_sync.v index 4cf11f0c37..2ca3a72829 100644 --- a/test_regress/t/t_source_sync.v +++ b/test_regress/t/t_source_sync.v @@ -1,17 +1,5 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Use this file as a template for submitting bugs, etc. -// This module takes a single clock input, and should either -// $write("*-* All Finished *-*\n"); -// $finish; -// on success, or $stop. -// -// The code as shown applies a random vector to the Test -// module, then calculates a CRC on the Test module's outputs. -// -// **If you do not wish for your code to be released to the public -// please note it here, otherwise:** -// // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Dan Petrisko. // SPDX-License-Identifier: CC0-1.0 From ef1b65e187487788666fdb5a2cb885f05ecbf7e0 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Tue, 6 Jul 2021 17:21:52 -0700 Subject: [PATCH 4/4] Updating out file --- test_regress/t/t_source_sync.out | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/test_regress/t/t_source_sync.out b/test_regress/t/t_source_sync.out index 257e767bd9..92dd48e27f 100644 --- a/test_regress/t/t_source_sync.out +++ b/test_regress/t/t_source_sync.out @@ -1,7 +1,7 @@ -%Error: t/t_source_sync.v:20:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';' - 20 | logic clk /*verilator clocker*/ ; +%Error: t/t_source_sync.v:8:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';' + 8 | logic clk /*verilator clocker*/ ; | ^~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_source_sync.v:22:1: syntax error, unexpected '}' - 22 | } ss_s; +%Error: t/t_source_sync.v:10:1: syntax error, unexpected '}' + 10 | } ss_s; | ^ %Error: Exiting due to