From 04af35344f1c417a60e47b49bdfdc50a47257be0 Mon Sep 17 00:00:00 2001
From: amin1377 <amin1377.mohaghegh@gmail.com>
Date: Sat, 5 Aug 2023 10:28:15 -0400
Subject: [PATCH] Add MIT license

---
 index.md | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/index.md b/index.md
index e1a6d54..68e3ecb 100644
--- a/index.md
+++ b/index.md
@@ -2,7 +2,9 @@
 layout: default
 ---
 
-The Verilog to Routing (VTR) project provides open-source CAD tools for FPGA architecture and CAD research.
+The Verilog to Routing (VTR) project provides open-source CAD tools for FPGA architecture and CAD research. This project, along with the benchmark suites, is released under the MIT license. This means that you are free to use, modify, and distribute the software and benchmark files, subject to the terms and conditions of the MIT license.
+
+
 
 <figure style="float:right">
     <img src='/img/vpr_placement.png' alt='VPR Placement' width="350px" />