From 68d9a9653a1f4406d08a111c9d7b1c01d147974d Mon Sep 17 00:00:00 2001 From: dani <17553473+poname@users.noreply.github.com> Date: Mon, 13 Feb 2023 16:44:20 -0400 Subject: [PATCH] fixed --- .github/labeler.yml | 5 ++ vtr_flow/parse/parse_config/adders.txt | 2 +- vtr_flow/parse/parse_config/common/parmys.txt | 4 ++ vtr_flow/parse/parse_config/common/yosys.txt | 4 -- .../parse_config/vpr_fixed_chan_width.txt | 2 +- vtr_flow/parse/parse_config/vpr_no_timing.txt | 2 +- vtr_flow/parse/parse_config/vpr_standard.txt | 2 +- .../freecores/config/config.txt | 36 +++++++++++ .../freecores/config/golden_results.txt | 7 +++ .../hdl_include/config/config.txt | 42 ------------- .../hdl_include/config/golden_results.txt | 2 - .../parmys_reg_basic/koios/config/config.txt | 49 +++++++++++++++ .../koios/config/golden_results.txt | 13 ++++ .../parmys_reg_basic/task_list.txt | 5 +- .../ultraembedded/config/config.txt | 36 +++++++++++ .../ultraembedded/config/golden_results.txt | 6 ++ .../vexriscv/config/config.txt | 59 +++++++++++++++++++ .../vexriscv/config/golden_results.txt | 13 ++++ .../vtr_benchmarks/config/config.txt | 6 +- .../vtr_benchmarks/config/golden_results.txt | 42 ++++++------- yosys/CMakeLists.txt | 4 +- 21 files changed, 263 insertions(+), 78 deletions(-) create mode 100644 vtr_flow/parse/parse_config/common/parmys.txt delete mode 100644 vtr_flow/parse/parse_config/common/yosys.txt create mode 100644 vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/golden_results.txt delete mode 100644 vtr_flow/tasks/regression_tests/parmys_reg_basic/hdl_include/config/config.txt delete mode 100644 vtr_flow/tasks/regression_tests/parmys_reg_basic/hdl_include/config/golden_results.txt create mode 100644 vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/golden_results.txt create mode 100644 vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/golden_results.txt create mode 100644 vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/golden_results.txt diff --git a/.github/labeler.yml b/.github/labeler.yml index 823c32de45e..a9540320cfd 100644 --- a/.github/labeler.yml +++ b/.github/labeler.yml @@ -21,6 +21,11 @@ Odin: - odin_ii/**/* - odin2_helper/* - odin2_helper/**/* +Parmys: + - parmys/* + - parmys/**/* + - yosys/* + - yosys/**/* VPR: - vpr/* - vpr/**/* diff --git a/vtr_flow/parse/parse_config/adders.txt b/vtr_flow/parse/parse_config/adders.txt index d3f685bbaaa..41438464e84 100644 --- a/vtr_flow/parse/parse_config/adders.txt +++ b/vtr_flow/parse/parse_config/adders.txt @@ -1,6 +1,6 @@ %include "common/vtr_flow.txt" %include "common/odin.txt" -%include "common/yosys.txt" +%include "common/parmys.txt" %include "common/abc.txt" %include "common/ace.txt" diff --git a/vtr_flow/parse/parse_config/common/parmys.txt b/vtr_flow/parse/parse_config/common/parmys.txt new file mode 100644 index 00000000000..35c3eedff92 --- /dev/null +++ b/vtr_flow/parse/parse_config/common/parmys.txt @@ -0,0 +1,4 @@ +#Parmys Run-time Metrics +parmys_synth_time;parmys.out;\s*User time \(seconds\): (.*) +max_parmys_mem;parmys.out;\s*Maximum resident set size \(kbytes\): (\d+) + diff --git a/vtr_flow/parse/parse_config/common/yosys.txt b/vtr_flow/parse/parse_config/common/yosys.txt deleted file mode 100644 index 94aadbd14a0..00000000000 --- a/vtr_flow/parse/parse_config/common/yosys.txt +++ /dev/null @@ -1,4 +0,0 @@ -#Yosys Run-time Metrics -yosys_synth_time;yosys.out;\s*User time \(seconds\): (.*) -max_yosys_mem;yosys.out;\s*Maximum resident set size \(kbytes\): (\d+) - diff --git a/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt b/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt index 1771a729954..cd21e4e4f48 100644 --- a/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt +++ b/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt @@ -3,7 +3,7 @@ %include "common/vtr_flow.txt" %include "common/odin.txt" -%include "common/yosys.txt" +%include "common/parmys.txt" %include "common/abc.txt" %include "common/ace.txt" diff --git a/vtr_flow/parse/parse_config/vpr_no_timing.txt b/vtr_flow/parse/parse_config/vpr_no_timing.txt index 247ee97de50..9eaacf30caa 100644 --- a/vtr_flow/parse/parse_config/vpr_no_timing.txt +++ b/vtr_flow/parse/parse_config/vpr_no_timing.txt @@ -1,6 +1,6 @@ %include "common/vtr_flow.txt" %include "common/odin.txt" -%include "common/yosys.txt" +%include "common/parmys.txt" %include "common/abc.txt" %include "common/ace.txt" diff --git a/vtr_flow/parse/parse_config/vpr_standard.txt b/vtr_flow/parse/parse_config/vpr_standard.txt index df882085f33..ecf38d37a8d 100644 --- a/vtr_flow/parse/parse_config/vpr_standard.txt +++ b/vtr_flow/parse/parse_config/vpr_standard.txt @@ -3,7 +3,7 @@ %include "common/vtr_flow.txt" %include "common/odin.txt" -%include "common/yosys.txt" +%include "common/parmys.txt" %include "common/abc.txt" %include "common/ace.txt" diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/config.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/config.txt new file mode 100644 index 00000000000..a301cae353d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/config.txt @@ -0,0 +1,36 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/freecores + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=aes_cipher.v +circuit_list_add=aes_inv_cipher.v +circuit_list_add=8051.v +circuit_list_add=ethmac.v +#circuit_list_add=dma_axi32.v +#circuit_list_add=dma_axi64.v +#circuit_list_add=i2c.v +circuit_list_add=mips_16.v +circuit_list_add=xtea.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -end parmys diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/golden_results.txt new file mode 100644 index 00000000000..c9831870b57 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/golden_results.txt @@ -0,0 +1,7 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml aes_cipher.v common 18.53 parmys 449.26 MiB -1 -1 15.62 460044 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml aes_inv_cipher.v common 18.57 parmys 456.23 MiB -1 -1 16.18 467176 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml 8051.v common 9.39 parmys 72.02 MiB -1 -1 7.45 73744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml ethmac.v common 10.80 parmys 105.79 MiB -1 -1 8.57 108328 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mips_16.v common 2.22 parmys 23.50 MiB -1 -1 0.48 24064 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml xtea.v common 2.60 parmys 32.87 MiB -1 -1 0.78 33660 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/hdl_include/config/config.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/hdl_include/config/config.txt deleted file mode 100644 index 951328f4767..00000000000 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/hdl_include/config/config.txt +++ /dev/null @@ -1,42 +0,0 @@ -################################################################# -# Configuration file for running experiments # -# # -# This config file is testing the ability to specify include # -# files that should be passed to the VTR Yosys frontend with # -# the top module of the benchmark (ch_intrinsic_modified.v). # -# This is done by specifying two Verilog header files that # -# provide essential definitions, and memory_controller design # -# that provides the design of an internal component for # -# "ch_intrinsic_modified.v". If the include files are not # -# properly included during compilation the benchmark is # -# incomplete and the flow will error out. # -################################################################# - -# Path to directory of circuits to use -circuits_dir=benchmarks/hdl_include - -# Path to directory of includes circuits to use -includes_dir=benchmarks/hdl_include/include - -# Path to directory of architectures to use -archs_dir=arch/no_timing/memory_sweep - -# Add circuits to list to sweep -circuit_list_add=ch_intrinsics_modified.v - -# Add circuits to includes list to sweep -include_list_add=generic_definitions1.vh -include_list_add=generic_definitions2.vh -include_list_add=memory_controller.v - -# Add architectures to list to sweep -arch_list_add=k4_N10_memSize16384_memData64.xml - -# Parse info and how to parse -parse_file=vpr_no_timing.txt - -# How to parse QoR info -qor_parse_file=qor_no_timing.txt - -# Script parameters -script_params_common=-track_memory_usage --timing_analysis off diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/hdl_include/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/hdl_include/config/golden_results.txt deleted file mode 100644 index b9f5801ddec..00000000000 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/hdl_include/config/golden_results.txt +++ /dev/null @@ -1,2 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 3.16 vpr 60.85 MiB -1 -1 0.45 20340 3 0.11 -1 -1 36456 -1 -1 75 99 1 0 success 897b3a8 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:33:37 gh-actions-runner-vtr-auto-spawned23 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 62308 99 130 357 487 1 228 305 13 13 169 clb auto 22.3 MiB 0.07 528 60.8 MiB 0.18 0.00 26 1569 29 3.33e+06 2.37e+06 360896. 2135.48 1.17 diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/config.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/config.txt new file mode 100644 index 00000000000..2181bb3b386 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/config.txt @@ -0,0 +1,49 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog/koios + +# Path to directory of architectures to use +archs_dir=arch/COFFE_22nm + +# Directory containing the verilog includes file(s) +includes_dir=benchmarks/verilog/koios + +# Add circuits to list to sweep +circuit_list_add=tpu_like.small.os.v +circuit_list_add=tpu_like.small.ws.v +circuit_list_add=dla_like.small.v +circuit_list_add=bnn.v +circuit_list_add=attention_layer.v +circuit_list_add=conv_layer_hls.v +circuit_list_add=conv_layer.v +circuit_list_add=eltwise_layer.v +circuit_list_add=robot_rl.v +circuit_list_add=reduction_layer.v +circuit_list_add=spmv.v +circuit_list_add=softmax.v + +# Add architectures to list to sweep +arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml + +# Add include files to the list. +# Some benchmarks instantiate hard dsp and memory blocks +# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. +# The hard_block_include.v file +# defines this macros, thereby enabling instantiations of the hard blocks +include_list_add=hard_block_include.v + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -end parmys diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/golden_results.txt new file mode 100644 index 00000000000..08c9fbcd7f1 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/golden_results.txt @@ -0,0 +1,13 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 18.42 parmys 193.73 MiB -1 -1 15.54 198380 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 22.44 parmys 241.20 MiB -1 -1 19.26 246984 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 69.72 parmys 729.88 MiB -1 -1 64.55 747392 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 60.13 parmys 715.25 MiB -1 -1 55.57 732416 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 30.82 parmys 313.96 MiB -1 -1 28.88 321500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 20.67 parmys 260.07 MiB -1 -1 18.02 266312 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 16.96 parmys 147.62 MiB -1 -1 13.04 151160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 5.73 parmys 84.64 MiB -1 -1 5.38 86676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 17.37 parmys 241.69 MiB -1 -1 16.38 247488 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 21.40 parmys 298.70 MiB -1 -1 18.62 305872 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 14.77 parmys 186.96 MiB -1 -1 10.43 191448 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 16.97 parmys 289.46 MiB -1 -1 12.38 296404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/task_list.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/task_list.txt index ce194007a52..9812e0e24f5 100644 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/task_list.txt +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/task_list.txt @@ -1,2 +1,5 @@ +regression_tests/parmys_reg_basic/koios/ regression_tests/parmys_reg_basic/vtr_benchmarks/ -regression_tests/parmys_reg_basic/hdl_include +regression_tests/parmys_reg_basic/ultraembedded/ +regression_tests/parmys_reg_basic/vexriscv/ +regression_tests/parmys_reg_basic/freecores/ diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/config.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/config.txt new file mode 100644 index 00000000000..5bff3b6e5cf --- /dev/null +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/config.txt @@ -0,0 +1,36 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/ultraembedded + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +#circuit_list_add=audio_core.v +circuit_list_add=enet_core.v +#circuit_list_add=ft60x_axi_core.v +#circuit_list_add=jpeg_core.v +circuit_list_add=mmc_core.v +#circuit_list_add=mpx_core.v +circuit_list_add=soc_core.v +circuit_list_add=uriscv_core.v +circuit_list_add=usb_uart_core.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -end parmys diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/golden_results.txt new file mode 100644 index 00000000000..3f32a270af0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/golden_results.txt @@ -0,0 +1,6 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml enet_core.v common 3.39 parmys 44.49 MiB -1 -1 1.96 45560 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mmc_core.v common 3.20 parmys 47.88 MiB -1 -1 2.88 49024 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml soc_core.v common 4.29 parmys 54.51 MiB -1 -1 3.77 55820 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml uriscv_core.v common 5.90 parmys 59.29 MiB -1 -1 3.89 60708 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml usb_uart_core.v common 5.90 parmys 47.80 MiB -1 -1 3.79 48952 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/config.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/config.txt new file mode 100644 index 00000000000..89248eddc1a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/config.txt @@ -0,0 +1,59 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/vexriscv + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +#circuit_list_add=BrieyDe0Nano.v +#circuit_list_add=Briey.v +#circuit_list_add=BrieyWithMemoryInit.v +#circuit_list_add=MuraxCfu.v +#circuit_list_add=MuraxDhrystoneReady.v +#circuit_list_add=MuraxFast.v +#circuit_list_add=Murax.v +#circuit_list_add=MuraxWithRamInit.v +circuit_list_add=VexRiscvFullNoMmuMaxPerf.v +circuit_list_add=VexRiscvFullNoMmuNoCache.v +circuit_list_add=VexRiscvFullNoMmu.v +circuit_list_add=VexRiscvFull.v +circuit_list_add=VexRiscvLinuxBalancedSmp.v +circuit_list_add=VexRiscvLinuxBalanced.v +#circuit_list_add=VexRiscvLinuxFpuSmpNoDecoder.v +#circuit_list_add=VexRiscvLinuxFpuSmpStupidDecoder.v +#circuit_list_add=VexRiscvLinuxFpuSmp.v +#circuit_list_add=VexRiscvMsuI4D4.v +circuit_list_add=VexRiscvNoCacheNoMmuMaxPerf.v +circuit_list_add=VexRiscvSecure.v +circuit_list_add=VexRiscvSmallAndProductiveICache.v +circuit_list_add=VexRiscvSmallAndProductive.v +circuit_list_add=VexRiscvSmallestNoCsr.v +circuit_list_add=VexRiscvSmallest.v +#circuit_list_add=VexRiscvThreeStagesBar.v +#circuit_list_add=VexRiscvThreeStagesMDfast.v +#circuit_list_add=VexRiscvThreeStagesMD.v +#circuit_list_add=VexRiscvThreeStages.v +#circuit_list_add=VexRiscvTwoStagesBar.v +#circuit_list_add=VexRiscvTwoStagesMDfast.v +#circuit_list_add=VexRiscvTwoStagesMD.v +#circuit_list_add=VexRiscvTwoStages.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -end parmys diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/golden_results.txt new file mode 100644 index 00000000000..ea3bc687884 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/golden_results.txt @@ -0,0 +1,13 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmuMaxPerf.v common 7.86 parmys 58.63 MiB -1 -1 5.42 60040 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmuNoCache.v common 4.05 parmys 52.39 MiB -1 -1 3.28 53652 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmu.v common 7.24 parmys 58.08 MiB -1 -1 5.82 59472 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFull.v common 8.84 parmys 65.60 MiB -1 -1 7.43 67172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvLinuxBalancedSmp.v common 12.34 parmys 82.25 MiB -1 -1 11.02 84220 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvLinuxBalanced.v common 10.81 parmys 78.95 MiB -1 -1 9.63 80848 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvNoCacheNoMmuMaxPerf.v common 6.70 parmys 54.23 MiB -1 -1 4.96 55528 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSecure.v common 13.41 parmys 90.82 MiB -1 -1 10.93 93004 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallAndProductiveICache.v common 4.27 parmys 39.73 MiB -1 -1 2.03 40684 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallAndProductive.v common 4.27 parmys 38.98 MiB -1 -1 2.00 39912 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallestNoCsr.v common 3.76 parmys 34.54 MiB -1 -1 1.53 35372 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallest.v common 4.27 parmys 36.97 MiB -1 -1 1.92 37856 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/config.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/config.txt index 4c2d866dace..990b363c5c6 100644 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/config.txt +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/config.txt @@ -29,8 +29,8 @@ circuit_list_add=stereovision1.v circuit_list_add=stereovision2.v circuit_list_add=stereovision3.v circuit_list_add=LU8PEEng.v -#circuit_list_add=LU32PEEng.v -#circuit_list_add=mcml.v +circuit_list_add=LU32PEEng.v +circuit_list_add=mcml.v # Add architectures to list to sweep arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml @@ -45,4 +45,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 +script_params=-track_memory_usage -end parmys diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/golden_results.txt index 46c0fca8936..e4b1d588da3 100644 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/golden_results.txt @@ -1,20 +1,22 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 391.33 vpr 238.61 MiB -1 -1 23.61 123568 20 64.69 -1 -1 71672 -1 -1 847 133 25 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 244332 133 179 14247 14104 1 7175 1184 36 36 1296 clb memory auto 149.2 MiB 34.28 121035 180.7 MiB 15.11 0.14 20.4852 -194013 -20.4852 20.4852 5.25 0.0377496 0.0330413 4.09711 3.41398 114 183293 48 7.21828e+07 5.93492e+07 9.23903e+06 7128.88 212.66 19.1388 16.0017 166531 14 30700 118209 33366716 7414475 23.4663 23.4663 -218364 -23.4663 0 0 1.16798e+07 9012.23 5.22 11.61 2.03619 1.81243 - k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 528.95 vpr 652.16 MiB -1 -1 43.44 621980 14 87.61 -1 -1 123032 -1 -1 2706 257 0 11 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 667816 257 32 35747 33389 1 19410 3006 63 63 3969 clb auto 367.4 MiB 74.88 253145 652.2 MiB 92.40 0.74 17.914 -23716.3 -17.914 17.914 53.76 0.103183 0.0838671 11.9395 9.82889 76 391211 29 2.36641e+08 1.50195e+08 2.05973e+07 5189.55 108.39 28.7273 23.9774 372269 19 96412 445708 25808244 4026029 20.2018 20.2018 -26336.3 -20.2018 0 0 2.57532e+07 6488.59 7.75 8.63 3.70892 3.30918 - k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 72.27 yosys 260.59 MiB -1 -1 11.03 266844 5 4.76 -1 -1 57484 -1 -1 494 36 0 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 139600 36 100 10175 7629 1 2793 630 28 28 784 clb auto 102.8 MiB 16.65 40935 136.3 MiB 4.16 0.04 13.7277 -2250.77 -13.7277 13.7277 2.75 0.0141846 0.0124364 1.52648 1.33405 70 69492 37 4.25198e+07 2.66236e+07 3.59791e+06 4589.17 21.01 4.74799 4.06299 60652 14 12555 64480 2572920 371127 15.397 15.397 -2596.71 -15.397 0 0 4.52633e+06 5773.37 1.17 0.94 0.553803 0.501759 - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 19.50 vpr 68.77 MiB -1 -1 12.60 47888 3 0.68 -1 -1 38536 -1 -1 44 196 1 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 70424 196 193 1202 1347 1 614 434 15 15 225 io auto 31.0 MiB 0.67 3011 68.8 MiB 0.51 0.01 2.01184 -980.486 -2.01184 2.01184 0.59 0.00182222 0.0015936 0.179244 0.157654 40 6048 22 1.03862e+07 2.91934e+06 568276. 2525.67 1.83 0.662727 0.596126 5465 12 1709 2607 217962 55517 2.51002 2.51002 -1171.5 -2.51002 0 0 712852. 3168.23 0.23 0.13 0.0846435 0.0798015 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.94 vpr 63.76 MiB -1 -1 0.26 21652 3 0.07 -1 -1 36416 -1 -1 68 99 1 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 65288 99 130 343 473 1 217 298 12 12 144 clb auto 25.8 MiB 0.21 547 63.8 MiB 0.16 0.00 1.48813 -111.528 -1.48813 1.48813 0.32 0.00045619 0.000399565 0.0388737 0.0341908 44 1353 8 5.66058e+06 4.21279e+06 360780. 2505.42 0.68 0.147128 0.132542 1113 11 372 617 24819 7606 1.88756 1.88756 -135.205 -1.88756 0 0 470760. 3269.17 0.14 0.03 0.0205006 0.019269 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 8.10 vpr 67.07 MiB -1 -1 0.33 25336 5 0.16 -1 -1 37408 -1 -1 31 162 0 5 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 68680 162 96 1067 884 1 657 294 16 16 256 mult_36 auto 29.4 MiB 0.37 4745 67.1 MiB 0.48 0.01 15.3124 -1132.64 -15.3124 15.3124 0.67 0.00157176 0.00139924 0.167895 0.150215 54 9978 39 1.21132e+07 3.65071e+06 835786. 3264.79 3.60 0.658145 0.599697 8578 18 2822 4431 1431948 365587 17.3056 17.3056 -1316.47 -17.3056 0 0 1.08607e+06 4242.47 0.33 0.36 0.0907615 0.0850593 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 15.02 vpr 65.43 MiB -1 -1 0.25 24036 5 0.12 -1 -1 36476 -1 -1 21 66 0 5 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67000 66 96 779 596 1 464 188 16 16 256 mult_36 auto 27.5 MiB 0.48 3773 65.4 MiB 0.29 0.00 11.7229 -729.673 -11.7229 11.7229 0.67 0.00109555 0.000980781 0.109535 0.0986273 48 8213 25 1.21132e+07 3.11177e+06 756778. 2956.16 10.72 0.678574 0.623282 7296 20 3403 7056 2501559 614761 12.9259 12.9259 -836.532 -12.9259 0 0 968026. 3781.35 0.31 0.56 0.0775653 0.0730537 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 97.18 vpr 309.04 MiB -1 -1 12.36 122160 5 3.70 -1 -1 47472 -1 -1 464 506 44 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 316460 506 553 3236 3734 1 2873 1567 50 50 2500 memory auto 56.1 MiB 4.38 15505 309.0 MiB 4.35 0.06 6.30539 -1950.52 -6.30539 6.30539 30.20 0.0154018 0.0138484 1.96789 1.76532 38 23631 16 1.47946e+08 4.91194e+07 6.86579e+06 2746.32 20.07 5.96646 5.48394 22632 16 4412 5516 3741903 989279 6.78035 6.78035 -2414.63 -6.78035 0 0 8.69102e+06 3476.41 4.32 1.54 0.724941 0.681435 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 18.79 vpr 69.52 MiB -1 -1 1.04 28708 2 0.11 -1 -1 37568 -1 -1 30 311 15 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 71188 311 156 1015 1158 1 965 512 28 28 784 memory auto 31.7 MiB 0.71 8739 69.5 MiB 0.85 0.01 3.86989 -4116.57 -3.86989 3.86989 2.71 0.00390228 0.00341486 0.385055 0.335219 40 15096 23 4.25198e+07 9.83682e+06 2.13295e+06 2720.61 7.28 1.41418 1.26253 14060 13 2941 3270 2497247 716267 4.39872 4.39872 -4975.37 -4.39872 -0.00135869 -0.00135869 2.67004e+06 3405.67 1.08 0.74 0.163132 0.151153 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 31.70 vpr 81.72 MiB -1 -1 5.64 55484 5 2.05 -1 -1 42364 -1 -1 175 193 5 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 83684 193 205 2771 2705 1 1368 578 20 20 400 memory auto 44.7 MiB 3.02 11136 81.7 MiB 1.67 0.02 5.22387 -2551.61 -5.22387 5.22387 1.26 0.0048368 0.00430375 0.571031 0.498925 56 19687 28 2.07112e+07 1.21714e+07 1.41661e+06 3541.53 12.81 2.50719 2.20483 17169 15 4647 11340 1242757 284331 6.06705 6.06705 -3063.93 -6.06705 0 0 1.80858e+06 4521.44 0.64 0.57 0.28349 0.26116 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 65.09 vpr 116.71 MiB -1 -1 5.00 65196 8 3.93 -1 -1 44628 -1 -1 247 385 2 1 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 119512 385 362 4417 4306 1 2360 997 26 26 676 io auto 58.7 MiB 6.30 29658 95.5 MiB 4.22 0.05 8.1341 -8918.18 -8.1341 8.1341 2.38 0.0102477 0.00888416 1.09583 0.966724 94 45846 20 3.69863e+07 1.48038e+07 3.99964e+06 5916.62 32.94 5.44912 4.83939 42860 16 10046 32710 3801291 733203 8.90022 8.90022 -10230.8 -8.90022 0 0 5.03706e+06 7451.27 1.84 1.35 0.53288 0.494485 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 24.14 vpr 82.33 MiB -1 -1 3.44 45336 3 0.77 -1 -1 40360 -1 -1 120 236 1 6 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84304 236 305 3195 3007 1 1534 668 19 19 361 io auto 45.5 MiB 2.24 12151 82.3 MiB 1.92 0.02 4.27652 -2642.42 -4.27652 4.27652 1.12 0.00517566 0.00456717 0.646869 0.57596 62 23629 24 1.72706e+07 9.39128e+06 1.42198e+06 3939.00 9.40 1.94364 1.73903 20659 16 6434 17007 3134575 708021 4.9842 4.9842 -3082.5 -4.9842 0 0 1.76637e+06 4892.99 0.65 0.94 0.302256 0.280118 - k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 16.54 vpr 79.74 MiB -1 -1 2.28 47236 4 1.73 -1 -1 41716 -1 -1 132 38 0 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 81652 38 36 2744 2493 1 1037 206 16 16 256 clb auto 42.9 MiB 1.93 8753 79.7 MiB 0.70 0.01 9.36767 -2501.88 -9.36767 9.36767 0.72 0.00362609 0.00300835 0.275692 0.233697 62 13665 39 1.21132e+07 7.11401e+06 968026. 3781.35 5.18 1.53768 1.3115 12472 21 4184 9814 370969 64997 10.7551 10.7551 -3015.2 -10.7551 0 0 1.20332e+06 4700.46 0.42 0.39 0.286746 0.256116 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 15.05 vpr 70.45 MiB -1 -1 2.71 35044 16 0.58 -1 -1 38648 -1 -1 61 45 3 1 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 72136 45 32 1188 1147 1 781 142 14 14 196 memory auto 32.8 MiB 1.93 6800 70.4 MiB 0.41 0.01 9.89355 -6235.34 -9.89355 9.89355 0.52 0.00235957 0.00187416 0.169872 0.141964 62 12793 31 9.20055e+06 5.32753e+06 735792. 3754.04 5.91 0.742137 0.637957 11210 16 3522 9234 1502472 381892 11.2832 11.2832 -7312.97 -11.2832 0 0 913676. 4661.61 0.30 0.51 0.153408 0.140186 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 79.60 vpr 225.71 MiB -1 -1 9.34 102480 5 8.39 -1 -1 69336 -1 -1 710 169 0 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 231124 169 197 23321 21461 1 6583 1076 33 33 1089 clb auto 173.5 MiB 10.79 40334 207.2 MiB 7.87 0.07 3.01283 -13314.4 -3.01283 3.01283 4.13 0.0264776 0.0227703 3.15518 2.64475 56 60875 27 6.0475e+07 3.82649e+07 4.09277e+06 3758.28 19.07 11.085 9.41515 56236 16 17062 27686 1028519 200024 3.71817 3.71817 -15844.9 -3.71817 0 0 5.21984e+06 4793.24 2.02 1.92 1.85117 1.68555 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 178.86 vpr 241.57 MiB -1 -1 8.35 124476 3 12.77 -1 -1 77388 -1 -1 680 115 0 40 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 247372 115 145 22868 19305 1 9678 980 40 40 1600 mult_36 auto 168.8 MiB 9.45 80732 202.4 MiB 9.16 0.10 4.99402 -21942.4 -4.99402 4.99402 6.18 0.0239433 0.019528 2.9241 2.41435 80 135696 48 9.16046e+07 5.24886e+07 8.41679e+06 5260.49 103.17 13.8407 11.7266 117593 17 34055 51734 19971192 4179690 5.30958 5.30958 -25329.8 -5.30958 0 0 1.06125e+07 6632.80 4.07 6.18 1.73317 1.57904 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 401.81 vpr 909.66 MiB -1 -1 11.78 197920 3 6.49 -1 -1 155540 -1 -1 1498 149 0 179 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 931496 149 182 55416 37075 1 28615 2008 80 80 6400 mult_36 auto 353.2 MiB 20.94 303233 909.7 MiB 47.91 0.37 14.3381 -49440 -14.3381 14.3381 84.89 0.0717821 0.0578119 9.50427 7.84131 100 405910 21 3.90281e+08 1.51617e+08 4.24662e+07 6635.34 147.08 24.2457 20.3899 389407 18 93954 111521 43422718 8861201 15.2309 15.2309 -56666 -15.2309 0 0 5.35781e+07 8371.59 20.80 9.99 2.48836 2.23469 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.15 vpr 63.23 MiB -1 -1 0.60 25680 4 0.16 -1 -1 36292 -1 -1 15 11 0 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64744 11 2 303 283 2 80 28 7 7 49 clb auto 24.9 MiB 0.19 267 63.2 MiB 0.02 0.00 1.86151 -149.067 -1.86151 1.77041 0.07 0.000236379 0.000178863 0.0102782 0.00868639 20 457 19 1.07788e+06 808410 52439.0 1070.18 0.08 0.0342395 0.0302305 388 18 286 492 8676 3081 2.28191 2.05156 -171.957 -2.28191 0 0 68696.0 1401.96 0.02 0.03 0.0224724 0.0202938 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 617.97 vpr 615.04 MiB -1 -1 55.54 455700 98 88.29 -1 -1 115608 -1 -1 2126 114 45 8 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 629796 114 102 35713 31804 1 16877 2395 56 56 3136 clb auto 342.6 MiB 63.63 225997 547.5 MiB 68.34 0.56 65.4237 -55589.5 -65.4237 65.4237 41.30 0.0898095 0.0706336 10.8204 8.77581 98 330954 34 1.8697e+08 1.42409e+08 2.01848e+07 6436.49 236.06 40.1544 32.9591 308907 21 64100 255615 40561760 9275477 74.7845 74.7845 -69505.8 -74.7845 0 0 2.55970e+07 8162.30 8.94 11.77 3.44705 3.03006 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 25.65 parmys 123.91 MiB -1 -1 21.77 126888 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 43.76 parmys 606.86 MiB -1 -1 42.07 621424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 12.44 parmys 247.64 MiB -1 -1 10.97 253584 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 13.76 parmys 49.20 MiB -1 -1 12.89 50380 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.39 parmys 24.57 MiB -1 -1 0.42 25160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 1.49 parmys 27.95 MiB -1 -1 0.49 28620 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 1.13 parmys 27.03 MiB -1 -1 0.37 27676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 13.73 parmys 122.91 MiB -1 -1 12.24 125864 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 2.32 parmys 31.36 MiB -1 -1 1.24 32108 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 8.34 parmys 56.53 MiB -1 -1 5.79 57884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 4.75 parmys 66.23 MiB -1 -1 3.94 67824 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 3.98 parmys 46.64 MiB -1 -1 3.41 47764 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 3.54 parmys 48.05 MiB -1 -1 2.40 49200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 3.97 parmys 37.42 MiB -1 -1 2.78 38320 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 10.26 parmys 103.86 MiB -1 -1 9.13 106348 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 7.96 parmys 124.97 MiB -1 -1 7.30 127968 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 12.34 parmys 197.93 MiB -1 -1 10.96 202676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.39 parmys 27.84 MiB -1 -1 0.57 28504 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 54.25 parmys 445.89 MiB -1 -1 50.87 456592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 127.93 parmys 1.40 GiB -1 -1 123.93 1466764 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 153.73 parmys 1.18 GiB -1 -1 150.40 1233652 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/yosys/CMakeLists.txt b/yosys/CMakeLists.txt index 55564ea4cd8..4e9b68a29ae 100644 --- a/yosys/CMakeLists.txt +++ b/yosys/CMakeLists.txt @@ -16,14 +16,14 @@ endif() # how to build the result of the library add_custom_command(OUTPUT yosys-bin - COMMAND ${MAKE_PROGRAM} "ENABLE_ABC=0" + COMMAND ${MAKE_PROGRAM} ENABLE_ABC=0 # -C ${CMAKE_CURRENT_BINARY_DIR} # -f ${CMAKE_CURRENT_SOURCE_DIR}/Makefile #(out-of-tree) build directory PREFIX=${CMAKE_BINARY_DIR} -j${CUSTOM_BUILD_PARALLEL_LEVEL} > /dev/null - COMMAND ${MAKE_PROGRAM} install + COMMAND ${MAKE_PROGRAM} install ENABLE_ABC=0 # -C ${CMAKE_CURRENT_BINARY_DIR} # -f ${CMAKE_CURRENT_SOURCE_DIR}/Makefile #(out-of-tree) build directory PREFIX=${CMAKE_BINARY_DIR}