module m(clk, we1, we2, data1, data2, out1, out2, addr1, addr2, sel);
input clk, we1, we2, sel;
input [4:0] addr1, addr2;
input [31:0] data1, data2;
output [31:0] out1, out2;

wire we11, we12, we21, we22;
wire [31:0] out11, out12, out21, out22;

assign we11 = (!sel ? we1 : 1'b0);
assign we12 = (!sel ? we2 : 1'b0);
assign we21 = (!sel ? 1'b0 : we1);
assign we22 = (!sel ? 1'b0 : we2);
assign out1 = (!sel ? out11 : out21);
assign out2 = (!sel ? out12 : out22);

dpr dpr1(clk, we11, we12, data1, data2, out11, out12, addr1, addr2);

// does not work: errors out with - Missing declaration of this symbol dual_port_ram
dpr dpr2(clk, we21, we22, data1, data2, out21, out22, addr1, addr2);

//dpr2 dpr2(clk, we21, we22, data1, data2, out21, out22, addr1, addr2);

endmodule

module dpr(clk, we1, we2, data1, data2, out1, out2, addr1, addr2);
input clk, we1, we2;
input [4:0] addr1, addr2;
input [31:0] data1, data2;
output [31:0] out1, out2;

dual_port_ram r(	
  .clk (clk),
  .we1(we1),
  .we2(we2),
  .data1(data1),
  .data2(data2),
  .out1(out1),
  .out2 (out2),
  .addr1(addr1),
  .addr2(addr2));

endmodule

//module dpr2(clk, we1, we2, data1, data2, out1, out2, addr1, addr2);
//input clk, we1, we2;
//input [4:0] addr1, addr2;
//input [31:0] data1, data2;
//output [31:0] out1, out2;
//
//dual_port_ram r(	
//  .clk (clk),
//  .we1(we1),
//  .we2(we2),
//  .data1(data1),
//  .data2(data2),
//  .out1(out1),
//  .out2 (out2),
//  .addr1(addr1),
//  .addr2(addr2));
//
//endmodule