diff --git a/ODIN_II/SRC/ast_elaborate.cpp b/ODIN_II/SRC/ast_elaborate.cpp
index 7798329939f..c38c8a63087 100644
--- a/ODIN_II/SRC/ast_elaborate.cpp
+++ b/ODIN_II/SRC/ast_elaborate.cpp
@@ -1840,15 +1840,14 @@ ast_node_t* reduce_expressions(ast_node_t* node, sc_hierarchy* local_ref, long*
 
                         long sc_spot = sc_lookup_string(local_symbol_table_sc, id);
                         if (sc_spot > -1) {
-                            bool is_signed = ((ast_node_t*)local_symbol_table_sc->data[sc_spot])->types.variable.is_signed;
-                            if (!is_signed) {
-                                VNumber* temp = node->children[1]->types.vnumber;
-                                VNumber* to_unsigned = new VNumber(V_UNSIGNED(*temp));
-                                node->children[1]->types.vnumber = to_unsigned;
-                                delete temp;
+                            operation_list signedness = ((ast_node_t*)local_symbol_table_sc->data[sc_spot])->types.variable.signedness;
+                            VNumber* old_value = node->children[1]->types.vnumber;
+                            if (signedness == UNSIGNED) {
+                                node->children[1]->types.vnumber = new VNumber(V_UNSIGNED(*old_value));
                             } else {
-                                /* leave as is */
+                                node->children[1]->types.vnumber = new VNumber(V_SIGNED(*old_value));
                             }
+                            delete old_value;
                         }
                     } else {
                         /* signed keyword is not supported, meaning unresolved values will already be handled as
@@ -2669,7 +2668,6 @@ void create_param_table_for_scope(ast_node_t* module_items, sc_hierarchy* local_
                     if (var_declare->types.variable.is_input
                         || var_declare->types.variable.is_output
                         || var_declare->types.variable.is_reg
-                        || var_declare->types.variable.is_integer
                         || var_declare->types.variable.is_genvar
                         || var_declare->types.variable.is_wire
                         || var_declare->types.variable.is_defparam)
diff --git a/ODIN_II/SRC/ast_util.cpp b/ODIN_II/SRC/ast_util.cpp
index 7e7de0996f4..0220f6d8213 100644
--- a/ODIN_II/SRC/ast_util.cpp
+++ b/ODIN_II/SRC/ast_util.cpp
@@ -166,10 +166,9 @@ ast_node_t* create_node_w_type(ids id, loc_t loc) {
     new_node->types.variable.is_inout = false;
     new_node->types.variable.is_wire = false;
     new_node->types.variable.is_reg = false;
-    new_node->types.variable.is_integer = false;
     new_node->types.variable.is_genvar = false;
     new_node->types.variable.is_memory = false;
-    new_node->types.variable.is_signed = false;
+    new_node->types.variable.signedness = UNSIGNED;
 
     return new_node;
 }
diff --git a/ODIN_II/SRC/enum_str.cpp b/ODIN_II/SRC/enum_str.cpp
index 79ac24bb7c5..bc9836d3782 100644
--- a/ODIN_II/SRC/enum_str.cpp
+++ b/ODIN_II/SRC/enum_str.cpp
@@ -1,8 +1,16 @@
 #include "odin_types.h"
 
+const char* ieee_std_STR[] = {
+    "1364-1995",
+    "1364-2001-noconfig",
+    "1364-2001",
+    "1364-2005",
+};
+
 const char* file_extension_supported_STR[] = {
     ".v",
-    ".vh"};
+    ".vh",
+};
 
 const char* edge_type_e_STR[] = {
     "UNDEFINED_SENSITIVITY",
@@ -100,7 +108,6 @@ const char* ids_STR[] = {
     "INOUT",
     "WIRE",
     "REG",
-    "INTEGER",
     "GENVAR",
     "PARAMETER",
     "LOCALPARAM",
diff --git a/ODIN_II/SRC/include/odin_types.h b/ODIN_II/SRC/include/odin_types.h
index 22e4b6a2cb8..299b4c61484 100644
--- a/ODIN_II/SRC/include/odin_types.h
+++ b/ODIN_II/SRC/include/odin_types.h
@@ -146,6 +146,8 @@ struct global_args_t {
 /**
  * defined in enum_str.cpp
  */
+extern const char* ieee_std_STR[];
+
 extern const char* file_extension_supported_STR[];
 
 extern const char* ZERO_GND_ZERO;
@@ -159,6 +161,13 @@ extern const char* edge_type_e_STR[];
 extern const char* operation_list_STR[][2];
 extern const char* ids_STR[];
 
+enum ieee_std {
+    ieee_1995,
+    ieee_2001_noconfig,
+    ieee_2001,
+    ieee_2005
+};
+
 enum file_extension_supported {
     VERILOG,
     VERILOG_HEADER,
@@ -257,7 +266,6 @@ enum ids {
     INOUT,
     WIRE,
     REG,
-    INTEGER,
     GENVAR,
     PARAMETER,
     LOCALPARAM,
@@ -374,10 +382,9 @@ struct typ {
         short is_inout;
         short is_wire;
         short is_reg;
-        short is_integer;
         short is_genvar;
         short is_memory;
-        short is_signed;
+        operation_list signedness;
         VNumber* initial_value = nullptr;
     } variable;
     struct
diff --git a/ODIN_II/SRC/include/parse_making_ast.h b/ODIN_II/SRC/include/parse_making_ast.h
index f5c14622728..1a5384d985e 100644
--- a/ODIN_II/SRC/include/parse_making_ast.h
+++ b/ODIN_II/SRC/include/parse_making_ast.h
@@ -19,9 +19,9 @@ ast_node_t* newStringNode(char* num, loc_t loc);
 ast_node_t* newList(ids type_id, ast_node_t* expression, loc_t loc);
 ast_node_t* newList_entry(ast_node_t* concat_node, ast_node_t* expression);
 ast_node_t* newListReplicate(ast_node_t* exp, ast_node_t* child, loc_t loc);
-ast_node_t* markAndProcessPortWith(ids top_type, ids port_id, ids net_id, ast_node_t* port, bool is_signed);
-ast_node_t* markAndProcessParameterWith(ids id, ast_node_t* parameter, bool is_signed);
-ast_node_t* markAndProcessSymbolListWith(ids top_type, ids id, ast_node_t* symbol_list, bool is_signed);
+ast_node_t* markAndProcessPortWith(ids top_type, ids port_id, ids net_id, ast_node_t* port, operation_list signedness);
+ast_node_t* markAndProcessParameterWith(ids id, ast_node_t* parameter, operation_list signedness);
+ast_node_t* markAndProcessSymbolListWith(ids top_type, ids id, ast_node_t* symbol_list, operation_list signedness);
 
 /* EXPRESSIONS */
 ast_node_t* newArrayRef(char* id, ast_node_t* expression, loc_t loc);
diff --git a/ODIN_II/SRC/netlist_create_from_ast.cpp b/ODIN_II/SRC/netlist_create_from_ast.cpp
index caf1796d340..86934139b5f 100644
--- a/ODIN_II/SRC/netlist_create_from_ast.cpp
+++ b/ODIN_II/SRC/netlist_create_from_ast.cpp
@@ -735,7 +735,7 @@ void create_all_driver_nets_in_this_scope(char* instance_name_prefix, sc_hierarc
         oassert(local_symbol_table[i]->type == VAR_DECLARE || local_symbol_table[i]->type == BLOCKING_STATEMENT);
         if (
             /* all registers are drivers */
-            (local_symbol_table[i]->types.variable.is_reg) || (local_symbol_table[i]->types.variable.is_integer)
+            (local_symbol_table[i]->types.variable.is_reg)
             /* a wire that is an input can be a driver */
             || ((local_symbol_table[i]->types.variable.is_wire)
                 && (!local_symbol_table[i]->types.variable.is_input))
@@ -1248,7 +1248,7 @@ void create_symbol_table_for_scope(ast_node_t* module_items, sc_hierarchy* local
                         continue;
 
                     oassert(var_declare->type == VAR_DECLARE);
-                    oassert((var_declare->types.variable.is_input) || (var_declare->types.variable.is_output) || (var_declare->types.variable.is_reg) || (var_declare->types.variable.is_integer) || (var_declare->types.variable.is_genvar) || (var_declare->types.variable.is_wire));
+                    oassert((var_declare->types.variable.is_input) || (var_declare->types.variable.is_output) || (var_declare->types.variable.is_reg) || (var_declare->types.variable.is_genvar) || (var_declare->types.variable.is_wire));
 
                     if (var_declare->types.variable.is_input
                         && var_declare->types.variable.is_reg) {
@@ -1281,15 +1281,14 @@ void create_symbol_table_for_scope(ast_node_t* module_items, sc_hierarchy* local
                             /* check for an initial value and copy it over if found */
                             ((ast_node_t*)local_symbol_table_sc->data[sc_spot])->types.variable.initial_value = init_value;
                         } else if ((var_declare->types.variable.is_reg) || (var_declare->types.variable.is_wire)
-                                   || (var_declare->types.variable.is_integer) || (var_declare->types.variable.is_genvar)) {
+                                   || (var_declare->types.variable.is_genvar)) {
                             /* copy the output status over */
                             ((ast_node_t*)local_symbol_table_sc->data[sc_spot])->types.variable.is_wire = var_declare->types.variable.is_wire;
                             ((ast_node_t*)local_symbol_table_sc->data[sc_spot])->types.variable.is_reg = var_declare->types.variable.is_reg;
 
-                            ((ast_node_t*)local_symbol_table_sc->data[sc_spot])->types.variable.is_integer = var_declare->types.variable.is_integer;
                             /* check for an initial value and copy it over if found */
                             ((ast_node_t*)local_symbol_table_sc->data[sc_spot])->types.variable.initial_value = init_value;
-                        } else if (!var_declare->types.variable.is_integer) {
+                        } else {
                             abort();
                         }
                     } else {
@@ -1349,7 +1348,6 @@ void create_symbol_table_for_scope(ast_node_t* module_items, sc_hierarchy* local
                     var_declare->types.variable.is_wire = true;
                     var_declare->types.variable.is_reg = false;
 
-                    var_declare->types.variable.is_integer = false;
                     var_declare->types.variable.is_input = false;
 
                     allocate_children_to_node(var_declare, {node, NULL, NULL, NULL, NULL, NULL});
diff --git a/ODIN_II/SRC/parse_making_ast.cpp b/ODIN_II/SRC/parse_making_ast.cpp
index 0bddd35660f..234c48f8ad9 100644
--- a/ODIN_II/SRC/parse_making_ast.cpp
+++ b/ODIN_II/SRC/parse_making_ast.cpp
@@ -334,10 +334,9 @@ ast_node_t* resolve_ports(ids top_type, ast_node_t* symbol_list) {
                     /* net type */
                     symbol_list->children[j]->types.variable.is_wire = this_port->types.variable.is_wire;
                     symbol_list->children[j]->types.variable.is_reg = this_port->types.variable.is_reg;
-                    symbol_list->children[j]->types.variable.is_integer = this_port->types.variable.is_integer;
 
                     /* signedness */
-                    symbol_list->children[j]->types.variable.is_signed = this_port->types.variable.is_signed;
+                    symbol_list->children[j]->types.variable.signedness = this_port->types.variable.signedness;
 
                     /* range */
                     if (symbol_list->children[j]->children[1] == NULL) {
@@ -355,7 +354,8 @@ ast_node_t* resolve_ports(ids top_type, ast_node_t* symbol_list) {
                     }
 
                     /* error checking */
-                    symbol_list->children[j] = markAndProcessPortWith(MODULE, NO_ID, NO_ID, symbol_list->children[j], this_port->types.variable.is_signed);
+
+                    symbol_list->children[j] = markAndProcessPortWith(MODULE, NO_ID, NO_ID, symbol_list->children[j], this_port->types.variable.signedness);
                 }
             } else {
                 long sc_spot = -1;
@@ -414,9 +414,11 @@ ast_node_t* resolve_ports(ids top_type, ast_node_t* symbol_list) {
     return unprocessed_ports;
 }
 
-ast_node_t* markAndProcessPortWith(ids top_type, ids port_id, ids net_id, ast_node_t* port, bool is_signed) {
+ast_node_t* markAndProcessPortWith(ids top_type, ids port_id, ids net_id, ast_node_t* port, operation_list signedness) {
     oassert((top_type == MODULE || top_type == FUNCTION || top_type == TASK)
-            && "can only use MODULE, FUNCTION ot TASK as top type");
+            && "can only use MODULE, FUNCTION or TASK as top type");
+
+    oassert(signedness == UNSIGNED || signedness == SIGNED);
 
     long sc_spot;
     const char* top_type_name = NULL;
@@ -475,24 +477,6 @@ ast_node_t* markAndProcessPortWith(ids top_type, ids port_id, ids net_id, ast_no
             }
             port->types.variable.is_reg = true;
             port->types.variable.is_wire = false;
-            port->types.variable.is_integer = false;
-            break;
-
-        case INTEGER:
-            if (port_id == INPUT) {
-                error_message(AST, port->loc, "%s",
-                              "Input cannot be defined as an integer\n");
-            } else if (port_id == INOUT) {
-                error_message(AST, port->loc, "%s",
-                              "Inout cannot be defined as an integer\n");
-            } else if (port_id == OUTPUT) {
-                /* cannot support signed ports right now (integers are signed) */
-                error_message(AST, port->loc,
-                              "Odin does not handle signed ports (%s)\n", port->children[0]->types.identifier);
-            }
-            port->types.variable.is_integer = true;
-            port->types.variable.is_reg = false;
-            port->types.variable.is_wire = false;
             break;
 
         case WIRE:
@@ -503,7 +487,6 @@ ast_node_t* markAndProcessPortWith(ids top_type, ids port_id, ids net_id, ast_no
             }
             port->types.variable.is_wire = true;
             port->types.variable.is_reg = false;
-            port->types.variable.is_integer = false;
             break;
 
         default:
@@ -514,20 +497,15 @@ ast_node_t* markAndProcessPortWith(ids top_type, ids port_id, ids net_id, ast_no
             }
 
             if (port->types.variable.is_reg
-                && !(port->types.variable.is_wire)
-                && !(port->types.variable.is_integer)) {
+                && !(port->types.variable.is_wire)) {
                 temp_net_id = REG;
-            } else if (port->types.variable.is_integer
-                       && !(port->types.variable.is_wire)
-                       && !(port->types.variable.is_reg)) {
-                temp_net_id = INTEGER;
             } else if (port->types.variable.is_wire
-                       && !(port->types.variable.is_reg)
-                       && !(port->types.variable.is_integer)) {
+                       && !(port->types.variable.is_reg)) {
                 temp_net_id = WIRE;
             } else {
                 /* port cannot have more than one type */
-                oassert(!(port->types.variable.is_wire) && !(port->types.variable.is_reg) && !(port->types.variable.is_integer));
+                oassert(!(port->types.variable.is_wire)
+                        && !(port->types.variable.is_reg));
             }
 
             if (net_id == NO_ID) {
@@ -576,16 +554,16 @@ ast_node_t* markAndProcessPortWith(ids top_type, ids port_id, ids net_id, ast_no
             if (port->types.variable.is_input
                 && !(port->types.variable.is_output)
                 && !(port->types.variable.is_inout)) {
-                port = markAndProcessPortWith(top_type, INPUT, net_id, port, is_signed);
+                port = markAndProcessPortWith(top_type, INPUT, net_id, port, signedness);
             } else if (port->types.variable.is_output
                        && !(port->types.variable.is_input)
                        && !(port->types.variable.is_inout)) {
-                port = markAndProcessPortWith(top_type, OUTPUT, net_id, port, is_signed);
+                port = markAndProcessPortWith(top_type, OUTPUT, net_id, port, signedness);
             } else if (port->types.variable.is_inout
                        && !(port->types.variable.is_input)
                        && !(port->types.variable.is_output)) {
                 error_message(AST, port->loc, "Odin does not handle inouts (%s)\n", port->children[0]->types.identifier);
-                port = markAndProcessPortWith(top_type, INOUT, net_id, port, is_signed);
+                port = markAndProcessPortWith(top_type, INOUT, net_id, port, signedness);
             } else {
                 // shouldn't ever get here...
                 oassert(port->types.variable.is_input
@@ -596,19 +574,19 @@ ast_node_t* markAndProcessPortWith(ids top_type, ids port_id, ids net_id, ast_no
             break;
     }
 
-    if (is_signed) {
+    if (signedness == SIGNED) {
         /* cannot support signed ports right now */
-        error_message(AST, port->loc,
-                      "Odin does not handle signed ports (%s)\n", port->children[0]->types.identifier);
+        warning_message(AST, port->loc,
+                        "Odin does not handle signed ports (%s)\n", port->children[0]->types.identifier);
     }
+    port->types.variable.signedness = signedness;
 
-    port->types.variable.is_signed = is_signed;
     port->types.variable.is_port = true;
 
     return port;
 }
 
-ast_node_t* markAndProcessParameterWith(ids id, ast_node_t* parameter, bool is_signed) {
+ast_node_t* markAndProcessParameterWith(ids id, ast_node_t* parameter, operation_list signedness) {
     if (id == PARAMETER) {
         parameter->children[5]->types.variable.is_parameter = true;
         parameter->types.variable.is_parameter = true;
@@ -617,14 +595,15 @@ ast_node_t* markAndProcessParameterWith(ids id, ast_node_t* parameter, bool is_s
         parameter->types.variable.is_localparam = true;
     }
 
-    if (is_signed) {
+    oassert(signedness == SIGNED || signedness == UNSIGNED);
+    if (signedness == SIGNED) {
         /* cannot support signed parameters right now */
-        error_message(AST, parameter->loc,
-                      "Odin does not handle signed parameters (%s)\n", parameter->children[0]->types.identifier);
+        warning_message(AST, parameter->loc,
+                        "Odin does not handle signed parameters (%s)\n", parameter->children[0]->types.identifier);
     }
 
-    parameter->children[5]->types.variable.is_signed = is_signed;
-    parameter->types.variable.is_signed = is_signed;
+    parameter->children[5]->types.variable.signedness = signedness;
+    parameter->types.variable.signedness = signedness;
 
     long sc_spot = -1;
 
@@ -642,11 +621,13 @@ ast_node_t* markAndProcessParameterWith(ids id, ast_node_t* parameter, bool is_s
     return parameter;
 }
 
-ast_node_t* markAndProcessSymbolListWith(ids top_type, ids id, ast_node_t* symbol_list, bool is_signed) {
+ast_node_t* markAndProcessSymbolListWith(ids top_type, ids id, ast_node_t* symbol_list, operation_list signedness) {
     long i;
     ast_node_t* range_min = NULL;
     ast_node_t* range_max = NULL;
 
+    oassert(signedness == SIGNED || signedness == UNSIGNED);
+
     if (symbol_list) {
         if (symbol_list->children[0] && symbol_list->children[0]->children[1]) {
             range_max = resolve_symbol_node(symbol_list->children[0]->children[1]);
@@ -659,123 +640,63 @@ ast_node_t* markAndProcessSymbolListWith(ids top_type, ids id, ast_node_t* symbo
                 symbol_list->children[i]->children[2] = ast_node_deep_copy(range_min);
             }
 
-            if (top_type == MODULE || top_type == TASK) {
-                switch (id) {
-                    case PARAMETER:
-                    case LOCALPARAM: {
-                        markAndProcessParameterWith(id, symbol_list->children[i], is_signed);
-                        break;
+            if (signedness == SIGNED) {
+                /* cannot support signed ports right now */
+                warning_message(AST, symbol_list->children[i]->loc,
+                                "Odin does not handle signed %s (%s)\n", ids_STR[id], symbol_list->children[i]->children[0]->types.identifier);
+            }
+            symbol_list->children[i]->types.variable.signedness = signedness;
+
+            switch (id) {
+                case PARAMETER:
+                    if (!(top_type == MODULE || top_type == FUNCTION || top_type == TASK)) {
+                        error_message(AST, symbol_list->children[i]->loc, "%s",
+                                      "parameters can only appear in modules functions or task\n");
                     }
-                    case INPUT:
-                    case OUTPUT:
-                    case INOUT:
-                        symbol_list->children[i] = markAndProcessPortWith(top_type, id, NO_ID, symbol_list->children[i], is_signed);
-                        break;
-                    case WIRE:
-                        if (is_signed) {
-                            /* cannot support signed nets right now */
-                            error_message(AST, symbol_list->children[i]->loc,
-                                          "Odin does not handle signed nets (%s)\n", symbol_list->children[i]->children[0]->types.identifier);
-                        }
-                        symbol_list->children[i]->types.variable.is_wire = true;
-                        break;
-                    case REG:
-                        if (is_signed) {
-                            /* cannot support signed regs right now */
-                            error_message(AST, symbol_list->children[i]->loc,
-                                          "Odin does not handle signed regs (%s)\n", symbol_list->children[i]->children[0]->types.identifier);
-                        }
-                        symbol_list->children[i]->types.variable.is_reg = true;
-                        break;
-                    case INTEGER:
-                        oassert(is_signed && "Integers must always be signed");
-                        symbol_list->children[i]->types.variable.is_signed = is_signed;
-                        symbol_list->children[i]->types.variable.is_integer = true;
-                        break;
-                    case GENVAR:
-                        oassert(is_signed && "Genvars must always be signed");
-                        symbol_list->children[i]->types.variable.is_signed = is_signed;
-                        symbol_list->children[i]->types.variable.is_genvar = true;
-                        break;
-                    default:
-                        oassert(false);
-                }
-            } else if (top_type == FUNCTION) {
-                switch (id) {
-                    case PARAMETER:
-                    case LOCALPARAM: {
-                        markAndProcessParameterWith(id, symbol_list->children[i], is_signed);
-                        break;
+                    // fallthrough
+                case LOCALPARAM:
+                    markAndProcessParameterWith(id, symbol_list->children[i], signedness);
+                    break;
+                case OUTPUT:
+                case INOUT:
+                case INPUT:
+                    if (!(top_type == MODULE || top_type == FUNCTION || top_type == TASK)) {
+                        error_message(AST, symbol_list->children[i]->loc, "%s",
+                                      "ports can only appear in modules functions or task\n");
                     }
-                    case INPUT:
-                    case OUTPUT:
-                    case INOUT:
-                        symbol_list->children[i] = markAndProcessPortWith(top_type, id, NO_ID, symbol_list->children[i], is_signed);
-                        break;
-                    case WIRE:
+                    symbol_list->children[i] = markAndProcessPortWith(top_type, id, NO_ID, symbol_list->children[i], signedness);
+                    break;
+                case WIRE:
+                    /**
+                     * functions cannot have their wire initialized, 
+                     * TODO: should'nt this apply to all? 
+                     */
+                    if (top_type == FUNCTION) {
                         if ((symbol_list->children[i]->num_children == 6 && symbol_list->children[i]->children[5] != NULL)
                             || (symbol_list->children[i]->num_children == 8 && symbol_list->children[i]->children[7] != NULL)) {
                             error_message(AST, symbol_list->children[i]->loc, "%s",
                                           "Nets cannot be initialized\n");
                         }
-                        if (is_signed) {
-                            /* cannot support signed nets right now */
-                            error_message(AST, symbol_list->children[i]->loc,
-                                          "Odin does not handle signed nets (%s)\n", symbol_list->children[i]->children[0]->types.identifier);
-                        }
-                        symbol_list->children[i]->types.variable.is_wire = true;
-                        break;
-                    case REG:
-                        if (is_signed) {
-                            /* cannot support signed regs right now */
-                            error_message(AST, symbol_list->children[i]->loc,
-                                          "Odin does not handle signed regs (%s)\n", symbol_list->children[i]->children[0]->types.identifier);
-                        }
-                        symbol_list->children[i]->types.variable.is_reg = true;
-                        break;
-                    case INTEGER:
-                        oassert(is_signed && "Integers must always be signed");
-                        symbol_list->children[i]->types.variable.is_signed = is_signed;
-                        symbol_list->children[i]->types.variable.is_integer = true;
-                        break;
-                    default:
-                        oassert(false);
-                }
-            } else if (top_type == BLOCK) {
-                switch (id) {
-                    case LOCALPARAM: {
-                        markAndProcessParameterWith(id, symbol_list->children[i], is_signed);
-                        break;
                     }
-                    case WIRE:
-                        if (is_signed) {
-                            /* cannot support signed nets right now */
-                            error_message(AST, symbol_list->children[i]->loc,
-                                          "Odin does not handle signed nets (%s)\n", symbol_list->children[i]->children[0]->types.identifier);
-                        }
-                        symbol_list->children[i]->types.variable.is_wire = true;
-                        break;
-                    case REG:
-                        if (is_signed) {
-                            /* cannot support signed regs right now */
-                            error_message(AST, symbol_list->children[i]->loc,
-                                          "Odin does not handle signed regs (%s)\n", symbol_list->children[i]->children[0]->types.identifier);
-                        }
-                        symbol_list->children[i]->types.variable.is_reg = true;
-                        break;
-                    case INTEGER:
-                        oassert(is_signed && "Integers must always be signed");
-                        symbol_list->children[i]->types.variable.is_signed = is_signed;
-                        symbol_list->children[i]->types.variable.is_integer = true;
-                        break;
-                    case GENVAR:
-                        oassert(is_signed && "Genvars must always be signed");
-                        symbol_list->children[i]->types.variable.is_signed = is_signed;
-                        symbol_list->children[i]->types.variable.is_genvar = true;
-                        break;
-                    default:
-                        oassert(false);
-                }
+                    symbol_list->children[i]->types.variable.is_wire = true;
+                    break;
+                case REG:
+                    symbol_list->children[i]->types.variable.is_reg = true;
+                    break;
+                case GENVAR:
+                    /**
+                     * TODO: BLOCK can be part of a function, so it would now accept it.
+                     *  * This should be addressed more thoroughly than this
+                     */
+                    if (!(top_type == MODULE || top_type == BLOCK || top_type == TASK)) {
+                        error_message(AST, symbol_list->children[i]->loc, "%s",
+                                      "genvar can only appear in modules blocks or task\n");
+                    }
+                    oassert(signedness == SIGNED && "Genvars must always be signed");
+                    symbol_list->children[i]->types.variable.is_genvar = true;
+                    break;
+                default:
+                    oassert(false);
             }
         }
 
@@ -1368,7 +1289,7 @@ ast_node_t* newGateInstance(char* gate_instance_name, ast_node_t* expression1, a
     char* newChar = vtr::strdup(get_identifier(expression1));
     ast_node_t* newVar = newVarDeclare(newChar, NULL, NULL, NULL, NULL, NULL, loc);
     ast_node_t* newVarList = newList(VAR_DECLARE_LIST, newVar, loc);
-    ast_node_t* newVarMaked = markAndProcessSymbolListWith(MODULE, WIRE, newVarList, false);
+    ast_node_t* newVarMaked = markAndProcessSymbolListWith(MODULE, WIRE, newVarList, UNSIGNED);
     if (size_module_variables_not_defined == 0) {
         module_variables_not_defined = (ast_node_t**)vtr::calloc(1, sizeof(ast_node_t*));
     } else {
@@ -1403,7 +1324,7 @@ ast_node_t* newMultipleInputsGateInstance(char* gate_instance_name, ast_node_t*
 
     ast_node_t* newVarList = newList(VAR_DECLARE_LIST, newVar, loc);
 
-    ast_node_t* newVarMarked = markAndProcessSymbolListWith(MODULE, WIRE, newVarList, false);
+    ast_node_t* newVarMarked = markAndProcessSymbolListWith(MODULE, WIRE, newVarList, UNSIGNED);
 
     if (size_module_variables_not_defined == 0) {
         module_variables_not_defined = (ast_node_t**)vtr::calloc(1, sizeof(ast_node_t*));
@@ -1477,7 +1398,6 @@ ast_node_t* newVarDeclare(char* symbol, ast_node_t* expression1, ast_node_t* exp
 /*---------------------------------------------------------------------------------------------
  * (function: newIntegerTypeVarDeclare)
  *-------------------------------------------------------------------------------------------*/
-
 ast_node_t* newIntegerTypeVarDeclare(char* symbol, ast_node_t* /*expression1*/, ast_node_t* /*expression2*/, ast_node_t* expression3, ast_node_t* expression4, ast_node_t* value, loc_t loc) {
     if (!is_valid_identifier(symbol)) {
         error_message(AST, loc, "Invalid character in identifier (%s)\n", symbol);
@@ -1497,6 +1417,7 @@ ast_node_t* newIntegerTypeVarDeclare(char* symbol, ast_node_t* /*expression1*/,
 
     return new_node;
 }
+
 /*-----------------------------------------
  * ----------------------------------------------------
  * (function: newModule)
@@ -1610,10 +1531,6 @@ ast_node_t* newFunction(ast_node_t* function_return, ast_node_t* list_of_ports,
         warning_message(AST, loc, "%s", "ODIN II does not (yet) differentiate between automatic and static tasks & functions.IGNORING ");
     }
 
-    if (function_return->children[0]->types.variable.is_integer) {
-        warning_message(AST, loc, "%s", "ODIN_II does not fully support input/output integers in functions");
-    }
-
     if (list_of_ports == NULL) {
         list_of_ports = create_node_w_type(VAR_DECLARE_LIST, loc);
     }
diff --git a/ODIN_II/SRC/verilog_bison.y b/ODIN_II/SRC/verilog_bison.y
index e5ee2fe2cce..8c4d9a271b2 100644
--- a/ODIN_II/SRC/verilog_bison.y
+++ b/ODIN_II/SRC/verilog_bison.y
@@ -26,6 +26,8 @@ OTHER DEALINGS IN THE SOFTWARE.
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
+#include <stdbool.h>
+
 #include "odin_types.h"
 #include "odin_globals.h"
 #include "odin_error.h"
@@ -38,6 +40,8 @@ OTHER DEALINGS IN THE SOFTWARE.
 extern loc_t my_location;
 
 void yyerror(const char *str){	delayed_error_message(PARSER, my_location, "error in parsing: (%s)\n",str);}
+int ieee_filter(int ieee_version, int return_type);
+
 int yywrap(){	return 1;}
 int yylex(void);
 
@@ -53,32 +57,105 @@ int yylex(void);
 	char *str_value;
 	ast_node_t *node;
 	ids id;
+	operation_list op;
 }
+
+/* base types */
 %token <id_name> vSYMBOL_ID
 %token <num_value> vNUMBER vINT_NUMBER
 %token <str_value> vSTRING
-%token vALWAYS vAUTOMATIC vINITIAL vSPECIFY vAND vASSIGN vBEGIN vCASE vDEFAULT vELSE vEND vENDCASE
-%token vENDMODULE vENDSPECIFY vENDGENERATE vENDFUNCTION vENDTASK vIF vINOUT vINPUT vMODULE vGENERATE vFUNCTION vTASK
-%token vOUTPUT vPARAMETER vLOCALPARAM vPOSEDGE vXNOR vXOR vDEFPARAM voANDAND vNAND vNEGEDGE vNOR vNOT vOR vFOR vBUF
-%token voOROR voLTE voGTE voPAL voSLEFT voSRIGHT voASLEFT voASRIGHT voEQUAL voNOTEQUAL voCASEEQUAL
-%token voCASENOTEQUAL voXNOR voNAND voNOR vWHILE vINTEGER vGENVAR
-%token vPLUS_COLON vMINUS_COLON vSPECPARAM voUNSIGNED voSIGNED vSIGNED 
+
+/********************
+ * Restricted keywords 
+ */
+
+/* Unlabeled */
+%token vAUTOMATIC
+%token vDEFAULT
+%token vDESIGN
+%token vDISABLE
+%token vEVENT
+%token vFORCE
+%token vINCDIR
+%token vINCLUDE
+%token vINITIAL
+%token vINSTANCE
+%token vLIBLIST
+%token vLIBRARY
+%token vNOSHOWCANCELLED
+%token vPULSESTYLE_ONDETECT
+%token vPULSESTYLE_ONEVENT
+%token vRELEASE
+%token vSHOWCANCELLED
+%token vCELL
+%token vUSE
+
+/* interconnect */
+%token vINOUT vINPUT vOUTPUT
+
+/* vars */
+%token vDEFPARAM vLOCALPARAM vPARAMETER vREALTIME vSPECPARAM vTIME
+
+/* control flow */
+%token vELSE vFOR vFOREVER vFORK vJOIN vIF vIFNONE vREPEAT vWAIT vWHILE 
+
+/* logic gates */
+%token vAND vBUF vBUFIF0 vBUFIF1 vNAND vNOR vNOT vNOTIF0 vNOTIF1 vOR vXOR vXNOR
+
+/* data types */
+%token vINTEGER vREAL vSCALARED vSIGNED vVECTORED vUNSIGNED
+
+/* power level */
+%token vSMALL vMEDIUM vLARGE vHIGHZ0 vHIGHZ1 vPULL0 vPULL1 vPULLDOWN vPULLUP vSTRONG0 vSTRONG1 vSUPPLY0 vSUPPLY1 vWEAK0 vWEAK1
+
+/* Transistor level logic */
+%token vCMOS vNMOS vPMOS vRCMOS vRNMOS vRPMOS vRTRAN vRTRANIF0 vRTRANIF1 vTRAN vTRANIF0 vTRANIF1
+
+/* net types */
+%token vWIRE vWAND vWOR vTRI vTRI0 vTRI1 vTRIAND vTRIOR vTRIREG vUWIRE vNONE vREG
+
+/* Timing Related */
+%token vALWAYS vEDGE vNEGEDGE vPOSEDGE
+
+/* statements */
+%token vASSIGN vDEASSIGN
+
+/* Blocks */
+%token vBEGIN vEND
+%token vCASE vENDCASE /* related */ vCASEX vCASEZ
+%token vCONFIG vENDCONFIG
+%token vFUNCTION vENDFUNCTION
+%token vGENERATE vENDGENERATE /* related */  vGENVAR
+%token vMODULE vMACROMODULE vENDMODULE
+%token vPRIMITIVE vENDPRIMITIVE
+%token vSPECIFY vENDSPECIFY
+%token vTABLE vENDTABLE
+%token vTASK vENDTASK
+
+/* logical operators */
+%token voNOTEQUAL voEQUAL voCASEEQUAL voOROR voLTE voGTE voANDAND voANDANDAND voCASENOTEQUAL '!'
+
+/* bitwise operators */
+%token voXNOR voNAND voNOR '|' '^' '&' '~'
+
+/* arithmetic operators */
+%token voSLEFT voSRIGHT voASLEFT voASRIGHT '+' '-' '*' '/' '%'
+
+/* unclassified operator */
+%token voEGT voPLUSCOLON voMINUSCOLON '='
 
 /* catch special characters */
-%token '?' ':' '|' '^' '&' '<' '>' '+' '-' '*' '/' '%' '(' ')' '{' '}' '[' ']' '~' '!' ';' '#' ',' '.' '@' '='
+%token '?' ':' '<' '>' '(' ')' '{' '}' '[' ']' ';' '#' ',' '.' '@' 
 
 /* C functions */
-%token voFINISH voDISPLAY vCFUNC vCLOG2
+%token vsFINISH vsDISPLAY vsCLOG2 vsUNSIGNED vsSIGNED vsFUNCTION
 
-	/* preprocessor directives */
+/* preprocessor directives */
 %token preDEFAULT_NETTYPE
 
-	/* net types */
-%token netWIRE netTRI netTRI0 netTRI1 netWAND netWOR netTRIAND netTRIOR netTRIREG netUWIRE netNONE netREG
-
 %right '?' ':'
 %left voOROR
-%left voANDAND
+%left voANDAND voANDANDAND
 %left '|'
 %left '^' voXNOR voNOR
 %left '&' voNAND
@@ -129,6 +206,9 @@ int yylex(void);
 %type <node> list_of_generate_block_items generate_item generate_block_item generate loop_generate_construct if_generate_construct 
 %type <node> case_generate_construct case_generate_item_list case_generate_items generate_block generate_localparam_declaration generate_defparam_declaration
 
+/* capture wether an operation is signed or not */
+%type <op> var_signedness
+
 %%
 
 source_text:
@@ -159,11 +239,11 @@ module_parameters:
 	;
 
 list_of_parameter_declaration:
-	list_of_parameter_declaration ',' vPARAMETER vSIGNED variable	{$$ = newList_entry($1, markAndProcessParameterWith(PARAMETER, $5, true));}
-	| list_of_parameter_declaration ',' vPARAMETER variable			{$$ = newList_entry($1, markAndProcessParameterWith(PARAMETER, $4, false));}
-	| list_of_parameter_declaration ',' variable					{$$ = newList_entry($1, markAndProcessParameterWith(PARAMETER, $3, false));} 
-	| vPARAMETER vSIGNED variable									{$$ = newList(VAR_DECLARE_LIST, markAndProcessParameterWith(PARAMETER, $3, true), my_location);}
-	| vPARAMETER variable											{$$ = newList(VAR_DECLARE_LIST, markAndProcessParameterWith(PARAMETER, $2, false), my_location);}
+	list_of_parameter_declaration ',' vPARAMETER var_signedness variable	{$$ = newList_entry($1, markAndProcessParameterWith(PARAMETER, $5, $4));}
+	| list_of_parameter_declaration ',' vPARAMETER variable			{$$ = newList_entry($1, markAndProcessParameterWith(PARAMETER, $4, UNSIGNED));}
+	| list_of_parameter_declaration ',' variable					{$$ = newList_entry($1, markAndProcessParameterWith(PARAMETER, $3, UNSIGNED));} 
+	| vPARAMETER var_signedness variable									{$$ = newList(VAR_DECLARE_LIST, markAndProcessParameterWith(PARAMETER, $3, $2), my_location);}
+	| vPARAMETER variable											{$$ = newList(VAR_DECLARE_LIST, markAndProcessParameterWith(PARAMETER, $2, UNSIGNED), my_location);}
 	;
 
 module_ports:
@@ -178,11 +258,11 @@ list_of_port_declaration:
 	;
 	
 port_declaration:
-	net_direction net_types vSIGNED variable			{$$ = markAndProcessPortWith(MODULE, $1, $2, $4, true);}
-	| net_direction net_types variable					{$$ = markAndProcessPortWith(MODULE, $1, $2, $3, false);}
-	| net_direction variable							{$$ = markAndProcessPortWith(MODULE, $1, NO_ID, $2, false);}
-	| net_direction vINTEGER integer_type_variable		{$$ = markAndProcessPortWith(MODULE, $1, INTEGER, $3, true);}
-	| net_direction vSIGNED variable					{$$ = markAndProcessPortWith(MODULE, $1, NO_ID, $3, true);}
+	net_direction net_types var_signedness variable			{$$ = markAndProcessPortWith(MODULE, $1, $2, $4, $3);}
+	| net_direction net_types variable					{$$ = markAndProcessPortWith(MODULE, $1, $2, $3, UNSIGNED);}
+	| net_direction variable							{$$ = markAndProcessPortWith(MODULE, $1, NO_ID, $2, UNSIGNED);}
+	| net_direction vINTEGER integer_type_variable		{$$ = markAndProcessPortWith(MODULE, $1, REG, $3, SIGNED);}
+	| net_direction var_signedness variable					{$$ = markAndProcessPortWith(MODULE, $1, NO_ID, $3, $2);}
 	| variable											{$$ = $1;}
 	;
 
@@ -272,7 +352,7 @@ list_of_specify_items:
 	;
 
 specparam_declaration:
-	'(' primary voPAL expression ')' '=' expression ';'	{free_whole_tree($2); free_whole_tree($4); free_whole_tree($7); $$ = NULL;}
+	'(' primary voEGT expression ')' '=' expression ';'	{free_whole_tree($2); free_whole_tree($4); free_whole_tree($7); $$ = NULL;}
 	| vSPECPARAM variable_list ';'						{free_whole_tree($2); $$ = NULL;}
 	;
 	
@@ -282,24 +362,24 @@ list_of_function_items:
 	;
 
 task_input_declaration:
-	vINPUT net_declaration					{$$ = markAndProcessSymbolListWith(TASK,INPUT, $2, false);}
-	| vINPUT integer_declaration			{$$ = markAndProcessSymbolListWith(TASK,INPUT, $2, true);}
-	| vINPUT vSIGNED variable_list ';'		{$$ = markAndProcessSymbolListWith(TASK,INPUT, $3, true);}
-	| vINPUT variable_list ';'				{$$ = markAndProcessSymbolListWith(TASK,INPUT, $2, false);}
+	vINPUT net_declaration					{$$ = markAndProcessSymbolListWith(TASK,INPUT, $2, UNSIGNED);}
+	| vINPUT integer_declaration			{$$ = markAndProcessSymbolListWith(TASK,INPUT, $2, SIGNED);}
+	| vINPUT var_signedness variable_list ';'		{$$ = markAndProcessSymbolListWith(TASK,INPUT, $3, $2);}
+	| vINPUT variable_list ';'				{$$ = markAndProcessSymbolListWith(TASK,INPUT, $2, UNSIGNED);}
 	;
 
 task_output_declaration:
-	vOUTPUT net_declaration					{$$ = markAndProcessSymbolListWith(TASK,OUTPUT, $2, false);}
-	| vOUTPUT integer_declaration			{$$ = markAndProcessSymbolListWith(TASK,OUTPUT, $2, true);}
-	| vOUTPUT vSIGNED variable_list ';'		{$$ = markAndProcessSymbolListWith(TASK,OUTPUT, $3, true);}
-	| vOUTPUT variable_list ';'				{$$ = markAndProcessSymbolListWith(TASK,OUTPUT, $2, false);}
+	vOUTPUT net_declaration					{$$ = markAndProcessSymbolListWith(TASK,OUTPUT, $2, UNSIGNED);}
+	| vOUTPUT integer_declaration			{$$ = markAndProcessSymbolListWith(TASK,OUTPUT, $2, SIGNED);}
+	| vOUTPUT var_signedness variable_list ';'		{$$ = markAndProcessSymbolListWith(TASK,OUTPUT, $3, $2);}
+	| vOUTPUT variable_list ';'				{$$ = markAndProcessSymbolListWith(TASK,OUTPUT, $2, UNSIGNED);}
 	;
 
 task_inout_declaration:
-	vINOUT net_declaration					{$$ = markAndProcessSymbolListWith(TASK,INOUT, $2, false);}
-	| vINOUT integer_declaration			{$$ = markAndProcessSymbolListWith(TASK,INOUT, $2, true);}
-	| vINOUT vSIGNED variable_list ';'		{$$ = markAndProcessSymbolListWith(TASK,INOUT, $3, true);}
-	| vINOUT variable_list ';'				{$$ = markAndProcessSymbolListWith(TASK,INOUT, $2, false);}
+	vINOUT net_declaration					{$$ = markAndProcessSymbolListWith(TASK,INOUT, $2, UNSIGNED);}
+	| vINOUT integer_declaration			{$$ = markAndProcessSymbolListWith(TASK,INOUT, $2, SIGNED);}
+	| vINOUT var_signedness variable_list ';'		{$$ = markAndProcessSymbolListWith(TASK,INOUT, $3, $2);}
+	| vINOUT variable_list ';'				{$$ = markAndProcessSymbolListWith(TASK,INOUT, $2, UNSIGNED);}
 	;
 
 list_of_task_items:
@@ -329,29 +409,29 @@ task_item:
 	;
 
 function_input_declaration:
-	vINPUT vSIGNED variable_list ';'	{$$ = markAndProcessSymbolListWith(FUNCTION, INPUT, $3, true);}
-	| vINPUT variable_list ';'			{$$ = markAndProcessSymbolListWith(FUNCTION, INPUT, $2, false);}
-	| vINPUT function_integer_declaration ';' {$$ = markAndProcessSymbolListWith(FUNCTION, INPUT, $2, false);}
+	vINPUT var_signedness variable_list ';'          {$$ = markAndProcessSymbolListWith(FUNCTION, INPUT, $3, $2);}
+	| vINPUT variable_list ';'                {$$ = markAndProcessSymbolListWith(FUNCTION, INPUT, $2, UNSIGNED);}
+	| vINPUT function_integer_declaration ';' {$$ = markAndProcessSymbolListWith(FUNCTION, INPUT, $2, UNSIGNED);}
 	;
 
 parameter_declaration:
-	vPARAMETER vSIGNED variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,PARAMETER, $3, true);}
-	| vPARAMETER variable_list ';'			{$$ = markAndProcessSymbolListWith(MODULE,PARAMETER, $2, false);}
+	vPARAMETER var_signedness variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,PARAMETER, $3, $2);}
+	| vPARAMETER variable_list ';'			{$$ = markAndProcessSymbolListWith(MODULE,PARAMETER, $2, UNSIGNED);}
 	;
 
 task_parameter_declaration:
-	vPARAMETER vSIGNED variable_list ';'	{$$ = markAndProcessSymbolListWith(TASK,PARAMETER, $3, true);}
-	| vPARAMETER variable_list ';'			{$$ = markAndProcessSymbolListWith(TASK,PARAMETER, $2, false);}
+	vPARAMETER var_signedness variable_list ';'	{$$ = markAndProcessSymbolListWith(TASK,PARAMETER, $3, $2);}
+	| vPARAMETER variable_list ';'			{$$ = markAndProcessSymbolListWith(TASK,PARAMETER, $2, UNSIGNED);}
 	;
 
 localparam_declaration:
-	vLOCALPARAM vSIGNED variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,LOCALPARAM, $3, true);}
-	| vLOCALPARAM variable_list ';'			{$$ = markAndProcessSymbolListWith(MODULE,LOCALPARAM, $2, false);}
+	vLOCALPARAM var_signedness variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,LOCALPARAM, $3, $2);}
+	| vLOCALPARAM variable_list ';'			{$$ = markAndProcessSymbolListWith(MODULE,LOCALPARAM, $2, UNSIGNED);}
 	;
 
 generate_localparam_declaration:
-	vLOCALPARAM vSIGNED variable_list ';'	{$$ = markAndProcessSymbolListWith(BLOCK,LOCALPARAM, $3, true);}
-	| vLOCALPARAM variable_list ';'			{$$ = markAndProcessSymbolListWith(BLOCK,LOCALPARAM, $2, false);}
+	vLOCALPARAM var_signedness variable_list ';'	{$$ = markAndProcessSymbolListWith(BLOCK,LOCALPARAM, $3, $2);}
+	| vLOCALPARAM variable_list ';'			{$$ = markAndProcessSymbolListWith(BLOCK,LOCALPARAM, $2, UNSIGNED);}
 	;
 
 defparam_declaration:
@@ -363,29 +443,29 @@ generate_defparam_declaration:
 	;
 
 io_declaration:
-	net_direction net_declaration					{$$ = markAndProcessSymbolListWith(MODULE,$1, $2, false);}
-	| net_direction integer_declaration				{$$ = markAndProcessSymbolListWith(MODULE,$1, $2, true);}
-	| net_direction vSIGNED variable_list ';'		{$$ = markAndProcessSymbolListWith(MODULE,$1, $3, true);}
-	| net_direction variable_list ';'				{$$ = markAndProcessSymbolListWith(MODULE,$1, $2, false);}
+	net_direction net_declaration					{$$ = markAndProcessSymbolListWith(MODULE,$1, $2, UNSIGNED);}
+	| net_direction integer_declaration				{$$ = markAndProcessSymbolListWith(MODULE,$1, $2, SIGNED);}
+	| net_direction var_signedness variable_list ';'		{$$ = markAndProcessSymbolListWith(MODULE,$1, $3, $2);}
+	| net_direction variable_list ';'				{$$ = markAndProcessSymbolListWith(MODULE,$1, $2, UNSIGNED);}
 	;
 
 net_declaration:
-	net_types vSIGNED variable_list ';'				{$$ = markAndProcessSymbolListWith(MODULE, $1, $3, true);}
-	| net_types variable_list ';'					{$$ = markAndProcessSymbolListWith(MODULE, $1, $2, false);}
+	net_types var_signedness variable_list ';'				{$$ = markAndProcessSymbolListWith(MODULE, $1, $3, $2);}
+	| net_types variable_list ';'					{$$ = markAndProcessSymbolListWith(MODULE, $1, $2, UNSIGNED);}
 	;
 
 integer_declaration:
-	vINTEGER integer_type_variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,INTEGER, $2, true);}
+	vINTEGER integer_type_variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,REG, $2, SIGNED);}
 	;
 
 genvar_declaration:
-	vGENVAR integer_type_variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,GENVAR, $2, true);}
+	vGENVAR integer_type_variable_list ';'	{$$ = markAndProcessSymbolListWith(MODULE,GENVAR, $2, SIGNED);}
 	;
 
 function_return:
-	list_of_function_return_variable							{$$ = markAndProcessSymbolListWith(FUNCTION, OUTPUT, $1, false);}
-	| vSIGNED list_of_function_return_variable				{$$ = markAndProcessSymbolListWith(FUNCTION, OUTPUT, $2, true);}
-	| function_integer_declaration							{$$ = markAndProcessSymbolListWith(FUNCTION, OUTPUT, $1, false);}		
+	list_of_function_return_variable							{$$ = markAndProcessSymbolListWith(FUNCTION, OUTPUT, $1, UNSIGNED);}
+	| var_signedness list_of_function_return_variable				{$$ = markAndProcessSymbolListWith(FUNCTION, OUTPUT, $2, $1);}
+	| function_integer_declaration							{$$ = markAndProcessSymbolListWith(FUNCTION, OUTPUT, $1, UNSIGNED);}		
 	;
 
 list_of_function_return_variable:
@@ -398,7 +478,7 @@ function_return_variable:
 	;
 
 function_integer_declaration:
-	vINTEGER integer_type_variable_list 				{$$ = markAndProcessSymbolListWith(FUNCTION, INTEGER, $2, true);}
+	vINTEGER integer_type_variable_list 				{$$ = markAndProcessSymbolListWith(FUNCTION, REG, $2, SIGNED);}
 	;
 
 function_port_list:
@@ -757,9 +837,9 @@ expression:
 	| voXNOR  expression %prec UXNOR				{$$ = newUnaryOperation(BITWISE_XNOR, $2, my_location);}
 	| '!' expression %prec ULNOT					{$$ = newUnaryOperation(LOGICAL_NOT, $2, my_location);}
 	| '^' expression %prec UXOR						{$$ = newUnaryOperation(BITWISE_XOR, $2, my_location);}
-	| vCLOG2 '(' expression ')'						{$$ = newUnaryOperation(CLOG2, $3, my_location);}
-	| voUNSIGNED '(' expression ')'					{$$ = newUnaryOperation(UNSIGNED, $3, my_location);}
-	| voSIGNED '(' expression ')'					{$$ = newUnaryOperation(SIGNED, $3, my_location);}
+	| vsCLOG2 '(' expression ')'					{$$ = newUnaryOperation(CLOG2, $3, my_location);}
+	| vsUNSIGNED '(' expression ')'					{$$ = newUnaryOperation(UNSIGNED, $3, my_location);}
+	| vsSIGNED '(' expression ')'					{$$ = newUnaryOperation(SIGNED, $3, my_location);}
 	| expression voPOWER expression					{$$ = newBinaryOperation(POWER,$1, $3, my_location);}
 	| expression '*' expression						{$$ = newBinaryOperation(MULTIPLY, $1, $3, my_location);}
 	| expression '/' expression						{$$ = newBinaryOperation(DIVIDE, $1, $3, my_location);}
@@ -796,8 +876,8 @@ primary:
 	vSYMBOL_ID												{$$ = newSymbolNode($1, my_location);}
 	| vSYMBOL_ID '[' expression ']'							{$$ = newArrayRef($1, $3, my_location);}
 	| vSYMBOL_ID '[' expression ']' '[' expression ']'		{$$ = newArrayRef2D($1, $3, $6, my_location);}
-	| vSYMBOL_ID '[' expression vPLUS_COLON expression ']'	{$$ = newPlusColonRangeRef($1, $3, $5, my_location);}
-	| vSYMBOL_ID '[' expression vMINUS_COLON expression ']'	{$$ = newMinusColonRangeRef($1, $3, $5, my_location);}
+	| vSYMBOL_ID '[' expression voPLUSCOLON expression ']'	{$$ = newPlusColonRangeRef($1, $3, $5, my_location);}
+	| vSYMBOL_ID '[' expression voMINUSCOLON expression ']'	{$$ = newMinusColonRangeRef($1, $3, $5, my_location);}
 	| vSYMBOL_ID '[' expression ':' expression ']'			{$$ = newRangeRef($1, $3, $5, my_location);}
 	| vSYMBOL_ID '[' expression ':' expression ']' '[' expression ':' expression ']'	{$$ = newRangeRef2D($1, $3, $5, $8, $10, my_location);}
 	| '{' expression_list '}'								{$$ = $2; ($2)->types.concat.num_bit_strings = -1;}
@@ -809,12 +889,12 @@ expression_list:
 	;
 
 c_function:
-	voFINISH '(' expression ')'									{$$ = newCFunction(FINISH, $3, NULL, my_location);}
-	| voDISPLAY '(' expression ')'									{$$ = newCFunction(DISPLAY, $3, NULL, my_location);}
-	| voDISPLAY '(' expression ',' c_function_expression_list ')'	{$$ = newCFunction(DISPLAY, $3, $5, my_location); /* this fails for now */}
-	| vCFUNC '(' c_function_expression_list ')'					{$$ = free_whole_tree($3);}
-	| vCFUNC '(' ')'											{$$ = NULL;}
-	| vCFUNC													{$$ = NULL;}
+	vsFINISH '(' expression ')'									{$$ = newCFunction(FINISH, $3, NULL, my_location);}
+	| vsDISPLAY '(' expression ')'									{$$ = newCFunction(DISPLAY, $3, NULL, my_location);}
+	| vsDISPLAY '(' expression ',' c_function_expression_list ')'	{$$ = newCFunction(DISPLAY, $3, $5, my_location); /* this fails for now */}
+	| vsFUNCTION '(' c_function_expression_list ')'					{$$ = free_whole_tree($3);}
+	| vsFUNCTION '(' ')'											{$$ = NULL;}
+	| vsFUNCTION													{$$ = NULL;}
 	;
 
 c_function_expression_list:
@@ -823,21 +903,21 @@ c_function_expression_list:
 	;
 
 wire_types: 
-	netWIRE 														{ $$ = WIRE; }
-	| netTRI 														{ $$ = WIRE; }
-	| netTRI0 														{ $$ = WIRE; }
-	| netTRI1 														{ $$ = WIRE; }
-	| netWAND 														{ $$ = WIRE; }
-	| netTRIAND 													{ $$ = WIRE; }
-	| netWOR 														{ $$ = WIRE; }
-	| netTRIOR 														{ $$ = WIRE; }
-	| netTRIREG 													{ $$ = WIRE; }
-	| netUWIRE 														{ $$ = WIRE; }
-	| netNONE														{ $$ = WIRE; }
+	vWIRE 															{ $$ = WIRE; }
+	| vTRI 															{ $$ = WIRE; }
+	| vTRI0 														{ $$ = WIRE; }
+	| vTRI1 														{ $$ = WIRE; }
+	| vWAND 														{ $$ = WIRE; }
+	| vTRIAND 														{ $$ = WIRE; }
+	| vWOR 															{ $$ = WIRE; }
+	| vTRIOR 														{ $$ = WIRE; }
+	| vTRIREG 														{ $$ = WIRE; }
+	| vUWIRE 														{ $$ = WIRE; }
+	| vNONE															{ $$ = NO_ID; /* no type here to force an error */ }
 	;
 
 reg_types: 
-	netREG 															{ $$ = REG; }
+	vREG 															{ $$ = REG; }
 	;
 
 net_types:
@@ -851,4 +931,191 @@ net_direction:
 	| vINOUT														{ $$ = INOUT; }
 	;
 
+var_signedness:
+	vUNSIGNED														{ $$ = UNSIGNED; }
+	| vSIGNED														{ $$ = SIGNED; }
+	;
+	
 %%
+
+
+/**
+ * This functions filters types based on the standard defined,
+ **/
+int ieee_filter(int ieee_version, int return_type) {
+
+	switch(return_type) {
+		case voANDANDAND:	//fallthrough
+		case voPOWER:	//fallthrough
+		case voANDAND:	//fallthrough
+		case voOROR:	//fallthrough
+		case voLTE:	//fallthrough
+		case voEGT:	//fallthrough
+		case voGTE:	//fallthrough
+		case voSLEFT:	//fallthrough
+		case voSRIGHT:	//fallthrough
+		case voEQUAL:	//fallthrough
+		case voNOTEQUAL:	//fallthrough
+		case voCASEEQUAL:	//fallthrough
+		case voCASENOTEQUAL:	//fallthrough
+		case voXNOR:	//fallthrough
+		case voNAND:	//fallthrough
+		case voNOR:	//fallthrough
+		case vALWAYS:	//fallthrough
+		case vAND:	//fallthrough
+		case vASSIGN:	//fallthrough
+		case vBEGIN:	//fallthrough
+		case vBUF:	//fallthrough
+		case vBUFIF0:	//fallthrough
+		case vBUFIF1:	//fallthrough
+		case vCASE:	//fallthrough
+		case vCASEX:	//fallthrough
+		case vCASEZ:	//fallthrough
+		case vCMOS:	//fallthrough
+		case vDEASSIGN:	//fallthrough
+		case vDEFAULT:	//fallthrough
+		case vDEFPARAM:	//fallthrough
+		case vDISABLE:	//fallthrough
+		case vEDGE:	//fallthrough
+		case vELSE:	//fallthrough
+		case vEND:	//fallthrough
+		case vENDCASE:	//fallthrough
+		case vENDFUNCTION:	//fallthrough
+		case vENDMODULE:	//fallthrough
+		case vENDPRIMITIVE:	//fallthrough
+		case vENDSPECIFY:	//fallthrough
+		case vENDTABLE:	//fallthrough
+		case vENDTASK:	//fallthrough
+		case vEVENT:	//fallthrough
+		case vFOR:	//fallthrough
+		case vFORCE:	//fallthrough
+		case vFOREVER:	//fallthrough
+		case vFORK:	//fallthrough
+		case vFUNCTION:	//fallthrough
+		case vHIGHZ0:	//fallthrough
+		case vHIGHZ1:	//fallthrough
+		case vIF:	//fallthrough
+		case vIFNONE:	//fallthrough
+		case vINITIAL:	//fallthrough
+		case vINOUT:	//fallthrough
+		case vINPUT:	//fallthrough
+		case vINTEGER:	//fallthrough
+		case vJOIN:	//fallthrough
+		case vLARGE:	//fallthrough
+		case vMACROMODULE:	//fallthrough
+		case vMEDIUM:	//fallthrough
+		case vMODULE:	//fallthrough
+		case vNAND:	//fallthrough
+		case vNEGEDGE:	//fallthrough
+		case vNMOS:	//fallthrough
+		case vNOR:	//fallthrough
+		case vNOT:	//fallthrough
+		case vNOTIF0:	//fallthrough
+		case vNOTIF1:	//fallthrough
+		case vOR:	//fallthrough
+		case vOUTPUT:	//fallthrough
+		case vPARAMETER:	//fallthrough
+		case vPMOS:	//fallthrough
+		case vPOSEDGE:	//fallthrough
+		case vPRIMITIVE:	//fallthrough
+		case vPULL0:	//fallthrough
+		case vPULL1:	//fallthrough
+		case vPULLDOWN:	//fallthrough
+		case vPULLUP:	//fallthrough
+		case vRCMOS:	//fallthrough
+		case vREAL:	//fallthrough
+		case vREALTIME:	//fallthrough
+		case vREG:	//fallthrough
+		case vRELEASE:	//fallthrough
+		case vREPEAT:	//fallthrough
+		case vRNMOS:	//fallthrough
+		case vRPMOS:	//fallthrough
+		case vRTRAN:	//fallthrough
+		case vRTRANIF0:	//fallthrough
+		case vRTRANIF1:	//fallthrough
+		case vSCALARED:	//fallthrough
+		case vSMALL:	//fallthrough
+		case vSPECIFY:	//fallthrough
+		case vSPECPARAM:	//fallthrough
+		case vSTRONG0:	//fallthrough
+		case vSTRONG1:	//fallthrough
+		case vSUPPLY0:	//fallthrough
+		case vSUPPLY1:	//fallthrough
+		case vTABLE:	//fallthrough
+		case vTASK:	//fallthrough
+		case vTIME:	//fallthrough
+		case vTRAN:	//fallthrough
+		case vTRANIF0:	//fallthrough
+		case vTRANIF1:	//fallthrough
+		case vTRI:	//fallthrough
+		case vTRI0:	//fallthrough
+		case vTRI1:	//fallthrough
+		case vTRIAND:	//fallthrough
+		case vTRIOR:	//fallthrough
+		case vTRIREG:	//fallthrough
+		case vVECTORED:	//fallthrough
+		case vWAIT:	//fallthrough
+		case vWAND:	//fallthrough
+		case vWEAK0:	//fallthrough
+		case vWEAK1:	//fallthrough
+		case vWHILE:	//fallthrough
+		case vWIRE:	//fallthrough
+		case vWOR:	//fallthrough
+		case vXNOR:	//fallthrough
+		case vXOR: {
+			if(ieee_version < ieee_1995)
+				delayed_error_message(PARSER, my_location, "error in parsing: (%s) only exists in ieee 1995 or newer\n",return_type)
+			break;
+		}
+		case voASLEFT:	//fallthrough
+		case voASRIGHT:	//fallthrough
+		case voPLUSCOLON:   //fallthrough
+		case voMINUSCOLON:   //fallthrough
+		case vAUTOMATIC:	//fallthrough
+		case vENDGENERATE:	//fallthrough
+		case vGENERATE:	//fallthrough
+		case vGENVAR:	//fallthrough
+		case vLOCALPARAM:	//fallthrough
+		case vNOSHOWCANCELLED:	//fallthrough
+		case vPULSESTYLE_ONDETECT:	//fallthrough
+		case vPULSESTYLE_ONEVENT:	//fallthrough
+		case vSHOWCANCELLED:	//fallthrough
+		case vSIGNED:	//fallthrough
+		case vUNSIGNED: {
+			if(ieee_version < ieee_2001_noconfig)
+				delayed_error_message(PARSER, my_location, "error in parsing: (%s) only exists in ieee 2001-noconfig or newer\n",return_type)
+			break;
+		}
+		case vCELL:	//fallthrough
+		case vCONFIG:	//fallthrough
+		case vDESIGN:	//fallthrough
+		case vENDCONFIG:	//fallthrough
+		case vINCDIR:	//fallthrough
+		case vINCLUDE:	//fallthrough
+		case vINSTANCE:	//fallthrough
+		case vLIBLIST:	//fallthrough
+		case vLIBRARY:	//fallthrough
+		case vUSE: {
+			if(ieee_version < ieee_2001)
+				delayed_error_message(PARSER, my_location, "error in parsing: (%s) only exists in ieee 2001 or newer\n",return_type)
+			break;
+		}
+		case vUWIRE: {
+			if(ieee_version < ieee_2005)
+				delayed_error_message(PARSER, my_location, "error in parsing: (%s) only exists in ieee 2005 or newer\n",return_type)
+			break;
+		}
+		/* unsorted. TODO: actually sort these */
+		case vsCLOG2:
+		case vsUNSIGNED:	//fallthrough
+		case vsSIGNED:	//fallthrough
+		case vsFINISH:	//fallthrough
+		case vsDISPLAY:	//fallthrough
+		case vsFUNCTION:	//fallthrough
+		default: {
+			break;
+		}
+	}
+	return return_type;
+
+}
diff --git a/ODIN_II/SRC/verilog_flex.l b/ODIN_II/SRC/verilog_flex.l
index 5268306e50b..1e09bbc5bf3 100644
--- a/ODIN_II/SRC/verilog_flex.l
+++ b/ODIN_II/SRC/verilog_flex.l
@@ -38,28 +38,52 @@ OTHER DEALINGS IN THE SOFTWARE.
 
 #define RECURSIVE_LIMIT 256
 
-#define YY_USER_ACTION {my_location.col = current_yycolumn; current_yycolumn = yyleng;}
+#define YY_USER_ACTION {                                           \
+    my_location.col = current_yycolumn; current_yycolumn = yyleng; \
+    }
 
-/* the define below helps with watching the parser go token by token */
-#define UNSUPPORTED_TOKEN 	{ delayed_error_message(PARSER, my_location, "%s", "Unsuported token"); }
+#define TOP_STATE() top_flex_state("")
 
-#define _STATE_TOP(str)		{ BEGIN(_state_top(str)); }
-#define POP_STATE()			{ _pop_state(); _STATE_TOP("Popped to "); }
-#define PUSH_STATE(state)	{ _push_state(state); _STATE_TOP("Pushed to ");}
-#define CHANGE_STATE(state) { _pop_state(); _push_state(state); _STATE_TOP("Switched to "); }
+#define POP_STATE() {                    \
+    flex_state.pop_back();               \
+    BEGIN(top_flex_state("Popped to ")); \
+    }
+
+#define PUSH_STATE(state)    {            \
+    flex_state.push_back(state);         \
+    BEGIN(top_flex_state("Pushed to ")); \
+    }
+
+#define CHANGE_STATE(state) {              \
+    flex_state.pop_back();                 \
+    flex_state.push_back(state);           \
+    BEGIN(top_flex_state("Switched to ")); \
+    }
 
 struct defines_t 
 {
-	std::string name;
-	bool use_va_args;
-	std::vector<std::string> args;
-	std::string body;
+    std::string name;
+    bool use_va_args;
+    std::vector<std::string> args;
+    std::string body;
 };
 
+extern loc_t my_location;
+
+int current_yycolumn = 1;
+std::unordered_map<std::string, defines_t*> defines_map;
+defines_t *current_define = NULL;
+std::vector<int> current_include_stack;
+std::vector<std::string> current_args;
+std::string current_define_body;
+
+std::vector<int> flex_state = {};
+std::vector<int> ieee_state = {};
+
 void MP();
-int _state_top(const char *str);
-void _pop_state();	
-void _push_state(int state);
+
+int top_flex_state(const char *str);
+int top_ieee_state(const char *str);
 
 void push_include(const char *file_name);
 bool pop_include();
@@ -81,19 +105,24 @@ void define_arg_push_back(char c);
 void load_define(const char *str);
 void initialize_defaults();
 
-extern loc_t my_location;
-
-int current_yycolumn = 1;
-std::unordered_map<std::string, defines_t*> defines_map;
-defines_t *current_define = NULL;
-std::vector<int> current_include_stack;
-std::vector<int> state_stack = { 0 };
-std::vector<std::string> current_args;
-std::string current_define_body;
-
+int ieee_filter(int return_type);
 %}
 
-%x INCLUDE BRACKET_MATCH COMMENT MULTI_LINE_COMMENT DEFINE_BODY SKIP ELIFCONDITION NEG_CONDITION CONDITION DEFINE_REMOVAL VAR_PARSE PARSE_DEFINE DEFINE_ARGS
+/* %x INITIAL  == 0 ** bison create initial by default and starts with it */
+%x BRACKET_MATCH
+%x COMMENT
+%x MULTI_LINE_COMMENT
+%x DEFINE_BODY
+%x SKIP
+%x ELIFCONDITION
+%x NEG_CONDITION
+%x CONDITION
+%x DEFINE_REMOVAL
+%x VAR_PARSE
+%x PARSE_DEFINE
+%x DEFINE_ARGS
+%x INCLUDE 
+%x READ_IEEE
 
 %option noyywrap
 %option nounput
@@ -112,749 +141,792 @@ vINT [[:digit:]][[:digit:]_]*
 vWORD [[:alpha:]_][[:alnum:]_$]*
 defineWORD [[:alnum:]_$]+
 vSTR ["]([^\\\"]|\\.)*["]  
-vPUNCT 	[\?\:\|\^\&\<\>\-\*\/\%\(\)\{\}\[\]\~\!\;\#\,\.\@\=\+]
+vPUNCT [\?\:\|\^\&\<\>\-\*\/\%\(\)\{\}\[\]\~\!\;\#\,\.\@\=\+]
 
 %%
 
-	/*	unsupported Keywords		*/
-<INITIAL>"casex"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"casez"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"disable"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"edge"						{ UNSUPPORTED_TOKEN;}
-<INITIAL>"scalared"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"bufif0"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"bufif1"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"cmos"						{ UNSUPPORTED_TOKEN;}
-<INITIAL>"deassign"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"endprimitive"				{ UNSUPPORTED_TOKEN;}
-<INITIAL>"endtable"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"event"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"force"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"forever"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"fork"						{ UNSUPPORTED_TOKEN;}
-<INITIAL>"highz0"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"highz1"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"join"						{ UNSUPPORTED_TOKEN;}
-<INITIAL>"large"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"medium"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"nmos"						{ UNSUPPORTED_TOKEN;}
-<INITIAL>"notif0"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"notif1"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"pmos"						{ UNSUPPORTED_TOKEN;}
-<INITIAL>"primitive"				{ UNSUPPORTED_TOKEN;}
-<INITIAL>"pull0"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"pull1"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"pulldown"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"pullup"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"rcmos"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"release"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"repeat"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"rnmos"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"rpmos"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"rtran"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"rtranif0"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"rtranif1"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"small"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"strong0"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"strong1"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"supply0"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"supply1"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"table"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"time"						{ UNSUPPORTED_TOKEN;}
-<INITIAL>"tran"						{ UNSUPPORTED_TOKEN;}
-<INITIAL>"tranif0"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"tranif1"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"vectored"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"wait"						{ UNSUPPORTED_TOKEN;}
-<INITIAL>"weak0"					{ UNSUPPORTED_TOKEN;}
-<INITIAL>"weak1"					{ UNSUPPORTED_TOKEN;}
-
-	/* preproc helpers */
-<VAR_PARSE>{vWORD}					{ MP(); add_args_to_define(yytext); }
-<VAR_PARSE>"..."					{ MP(); add_args_to_define(yytext); }
-<VAR_PARSE>[\,]						{  }
-<VAR_PARSE>[\)]						{ CHANGE_STATE(DEFINE_BODY); }
-<PARSE_DEFINE>{defineWORD}[\(]		{ MP(); new_define_t(yytext); CHANGE_STATE(VAR_PARSE);}
-<PARSE_DEFINE>{defineWORD}			{ MP(); new_define_t(yytext); CHANGE_STATE(DEFINE_BODY);}
-<INITIAL>"`define"					{ MP(); PUSH_STATE(PARSE_DEFINE); }
-
-<DEFINE_REMOVAL>{vWORD}				{ MP(); free_define_t(yytext); POP_STATE();}
-<INITIAL>"`undef"					{ MP(); PUSH_STATE(DEFINE_REMOVAL); }
-
-<CONDITION>{vWORD}					{ MP(); CHANGE_STATE( ((ifdef(yytext))?  INITIAL: SKIP) ); }
-<NEG_CONDITION>{vWORD}				{ MP(); CHANGE_STATE( ((ifdef(yytext))?  SKIP: INITIAL) ); }
-
-	/* since the condition did not hold true, we evaluate these statement */
-<SKIP>"`elsif"						{ MP(); CHANGE_STATE(CONDITION); }
-<SKIP>"`else"						{ MP(); CHANGE_STATE(INITIAL);}
-
-	/* since the condition held true, we need to skip these */
-<INITIAL>"`elsif"					{ MP(); CHANGE_STATE(SKIP); }
-<INITIAL>"`else"					{ MP(); CHANGE_STATE(SKIP);}
-
-	/* entry point */
-<INITIAL>"`ifdef"					{ MP(); PUSH_STATE(CONDITION);}
-<INITIAL>"`ifndef"					{ MP(); PUSH_STATE(NEG_CONDITION);}
-
-	/* exit point */
-<INITIAL,SKIP>"`endif"				{ MP(); POP_STATE();}
-
-<INITIAL>"`include"             	{ MP(); PUSH_STATE(INCLUDE); }
-<INCLUDE>{vSTR}      				{ MP(); push_include(yytext); POP_STATE(); }
-
-<INITIAL>"`default_nettype"			{ MP(); return preDEFAULT_NETTYPE;}
-<INITIAL>"`resetall"				{ MP(); initialize_defaults();}
-
-	/* unsupported commands, we skip the rest of the line */
-<INITIAL>"`timescale"				{ MP(); PUSH_STATE(COMMENT); }
-<INITIAL>"`pragma"					{ MP(); PUSH_STATE(COMMENT); }
-<INITIAL>"`line"					{ MP(); PUSH_STATE(COMMENT); }
-<INITIAL>"`celldefine"				{ MP(); PUSH_STATE(COMMENT); }
-<INITIAL>"`endcelldefine"			{ MP(); PUSH_STATE(COMMENT); }
-<INITIAL>"`begin_keywords"			{ MP(); PUSH_STATE(COMMENT); }
-<INITIAL>"`end_keywords"			{ MP(); PUSH_STATE(COMMENT); }
-<INITIAL>"`nounconnected_drive"		{ MP(); PUSH_STATE(COMMENT); }
-<INITIAL>"`unconnected_drive"		{ MP(); PUSH_STATE(COMMENT); }
-
-
-<DEFINE_ARGS>[\)]					{ MP(); POP_STATE(); lex_string(get_complex_define().c_str()); }
-<DEFINE_ARGS>[\,]					{ MP(); next_define_arg(); }
-<BRACKET_MATCH>[\)]					{ MP(); POP_STATE(); define_arg_push_back(yytext[0]); }
-<DEFINE_ARGS,BRACKET_MATCH>[\(]		{ MP(); PUSH_STATE(BRACKET_MATCH); define_arg_push_back(yytext[0]);}
-<INITIAL>[\`]{vWORD}[\(]			{ MP(); load_define(yytext); PUSH_STATE(DEFINE_ARGS); }
-<INITIAL>[\`]{vWORD}				{ MP(); lex_string(get_simple_define(yytext).c_str());}
-
-
-	/* Begin Scoped items */
-<INITIAL>"begin"					{ MP(); push_scope(); return vBEGIN;}
-<INITIAL>"function"					{ MP(); push_scope(); return vFUNCTION;}
-<INITIAL>"module"					{ MP(); push_scope(); return vMODULE;}
-<INITIAL>"macromodule"				{ MP(); push_scope(); return vMODULE;}
-<INITIAL>"task"						{ MP(); push_scope(); return vTASK;}
-
-	/* End Scoped items */
-<INITIAL>"end"						{ MP(); return vEND;}
-<INITIAL>"endfunction"				{ MP(); return vENDFUNCTION;}
-<INITIAL>"endmodule"				{ MP(); return vENDMODULE;}
-<INITIAL>"endtask"					{ MP(); return vENDTASK;}
-
-	/*	Keywords	*/
-<INITIAL>"always"					{ MP(); return vALWAYS;}
-<INITIAL>"and"						{ MP(); return vAND;}
-<INITIAL>"assign"					{ MP(); return vASSIGN;}
-<INITIAL>"automatic"				{ MP(); return vAUTOMATIC;}
-<INITIAL>"case"						{ MP(); return vCASE;}
-<INITIAL>"default"					{ MP(); return vDEFAULT;}
-<INITIAL>"defparam"					{ MP(); return vDEFPARAM;}
-<INITIAL>"else"						{ MP(); return vELSE;}
-<INITIAL>"endcase"					{ MP(); return vENDCASE;}
-<INITIAL>"endspecify"				{ MP(); return vENDSPECIFY;}
-<INITIAL>"endgenerate"				{ MP(); return vENDGENERATE;}
-<INITIAL>"for"						{ MP(); return vFOR;}
-<INITIAL>"if"						{ MP(); return vIF;}
-<INITIAL>"initial"					{ MP(); return vINITIAL;}
-<INITIAL>"inout"					{ MP(); return vINOUT;}
-<INITIAL>"input"					{ MP(); return vINPUT;}
-<INITIAL>"integer"					{ MP(); return vINTEGER;}
-<INITIAL>"generate"					{ MP(); return vGENERATE;}
-<INITIAL>"genvar"					{ MP(); return vGENVAR;}
-<INITIAL>"nand"						{ MP(); return vNAND;}
-<INITIAL>"negedge"					{ MP(); return vNEGEDGE;}
-<INITIAL>"nor"						{ MP(); return vNOR;}
-<INITIAL>"not"						{ MP(); return vNOT;}
-<INITIAL>"or"						{ MP(); return vOR;}
-<INITIAL>"output"					{ MP(); return vOUTPUT;}
-<INITIAL>"parameter"				{ MP(); return vPARAMETER;}
-<INITIAL>"localparam"				{ MP(); return vLOCALPARAM;}
-<INITIAL>"posedge"					{ MP(); return vPOSEDGE;}
-<INITIAL>"signed"					{ MP(); return vSIGNED;}
-<INITIAL>"specify"					{ MP(); return vSPECIFY;}
-<INITIAL>"while"					{ MP(); return vWHILE;}
-<INITIAL>"xnor"						{ MP(); return vXNOR;}
-<INITIAL>"xor"						{ MP(); return vXOR;}
-<INITIAL>"specparam"				{ MP(); return vSPECPARAM;}
-<INITIAL>"buf"				        { MP(); return vBUF;}
-
-	/* Net types */
-<INITIAL>"wire"						{ MP(); return netWIRE;}
-<INITIAL>"tri"						{ MP(); return netTRI;}
-<INITIAL>"tri0"						{ MP(); return netTRI0;}
-<INITIAL>"tri1"						{ MP(); return netTRI1;}
-<INITIAL>"wand"						{ MP(); return netWAND;}
-<INITIAL>"wor"						{ MP(); return netWOR;}
-<INITIAL>"triand"					{ MP(); return netTRIAND;}
-<INITIAL>"trior"					{ MP(); return netTRIOR;}
-<INITIAL>"trireg"					{ MP(); return netTRIREG;}
-<INITIAL>"uwire"					{ MP(); return netUWIRE;}
-<INITIAL>"none"						{ MP(); return netNONE;}
-<INITIAL>"reg"						{ MP(); return netREG;}
-
-	/* Operators */	
-<INITIAL>"**"						{ MP(); return voPOWER;}
-<INITIAL>"&&"						{ MP(); return voANDAND;}
-<INITIAL>"||"						{ MP(); return voOROR;}
-<INITIAL>"<="						{ MP(); return voLTE;}
-<INITIAL>"=>"						{ MP(); return voPAL;}
-<INITIAL>">="						{ MP(); return voGTE;}
-<INITIAL>"<<"						{ MP(); return voSLEFT;}
-<INITIAL>"<<<"						{ MP(); return voASLEFT;}
-<INITIAL>">>"						{ MP(); return voSRIGHT;}
-<INITIAL>">>>"						{ MP(); return voASRIGHT;}
-<INITIAL>"=="						{ MP(); return voEQUAL;}
-<INITIAL>"!="						{ MP(); return voNOTEQUAL;}
-<INITIAL>"==="						{ MP(); return voCASEEQUAL;}
-<INITIAL>"!=="						{ MP(); return voCASENOTEQUAL;}
-<INITIAL>"^~"						{ MP(); return voXNOR;}
-<INITIAL>"~^"						{ MP(); return voXNOR;}
-<INITIAL>"~&"						{ MP(); return voNAND;}
-<INITIAL>"~|"						{ MP(); return voNOR;}
-<INITIAL>"+:"						{ MP(); return vPLUS_COLON;}
-<INITIAL>"-:"						{ MP(); return vMINUS_COLON;}
-
-	/*	unsupported Operators	*/
-<INITIAL>"&&&"						{ UNSUPPORTED_TOKEN;}
-
-	/*	C functions	*/	
-<INITIAL>"$clog2"					{ MP(); return vCLOG2;}
-<INITIAL>"$unsigned"				{ MP(); return voUNSIGNED;}
-<INITIAL>"$signed"					{ MP(); return voSIGNED;}
-<INITIAL>"$finish"					{ MP(); return voFINISH;}
-<INITIAL>"$display"					{ MP(); return voDISPLAY;}
-	/* catch all C functions */
-<INITIAL>[\$]{vWORD}				{ MP(); return vCFUNC;}
-
-	/* Integers */
-<INITIAL>{vINT}						{ MP(); yylval.num_value = vtr::strdup(yytext); return vINT_NUMBER; }
-	/* Strings */
-<INITIAL>{vSTR}						{ MP(); yylval.num_value = vtr::strdup(yytext); return vSTRING; }
-	/* Numbers */
-<INITIAL>[[:digit:]]*'[sS]?{vBIN}	{ MP(); yylval.num_value = vtr::strdup(yytext); return vNUMBER; }
-<INITIAL>[[:digit:]]*'[sS]?{vHEX}	{ MP(); yylval.num_value = vtr::strdup(yytext); return vNUMBER; }
-<INITIAL>[[:digit:]]*'[sS]?{vOCT}	{ MP(); yylval.num_value = vtr::strdup(yytext); return vNUMBER; }
-<INITIAL>[[:digit:]]*'[sS]?{vDEC}	{ MP(); yylval.num_value = vtr::strdup(yytext); return vNUMBER; }
-
-	/*	operands	*/
-<INITIAL>{vWORD}(\.{vWORD})*		{ MP(); yylval.id_name = vtr::strdup(yytext); return vSYMBOL_ID; }
-
-	/* return operators */
-<INITIAL>{vPUNCT}					{ MP(); return yytext[0]; }
-
-	/* general stuff */
-
-	/* single line comment */
-<*>[\/][\/]							{ 
-										int state = _state_top("");
-										if (state == DEFINE_BODY)
-										{
-											/**
-											* single line comments will automaticaly continue on if we
-											* escape the new line, to prevent issues, we stop processing the macro body
-											*/
-											finalize_define();
-											_pop_state();
-										}
-										if(state != COMMENT
-										&& state != MULTI_LINE_COMMENT)
-										{
-											PUSH_STATE(COMMENT);
-										}
-									}
-	/* multi line comment */
-<*>[\/][\*]							{ 
-										int state = _state_top("");
-										if(state != COMMENT
-										&& state != MULTI_LINE_COMMENT)
-										{
-											PUSH_STATE(MULTI_LINE_COMMENT);
-										}
-									}
-
-<MULTI_LINE_COMMENT>[\*][\/]			{ POP_STATE(); }
-
-<*>[[:blank:]]+						{ 	
-										int state = _state_top("");
-										if(state == DEFINE_BODY)
-										{
-											append_to_define_body(' ');
-										}
-										else if(state == DEFINE_ARGS
-										|| 		state == BRACKET_MATCH)
-										{
-											define_arg_push_back(yytext[0]);
-										} 
-									}
-
-<*><<EOF>>							{ if ( ! pop_include() ){ free_define_map(); yyterminate(); } }
-
-	/* skip escapped newline */
-<*>\\\r?\n							{ my_location.line++; my_location.col = 1; }
-
-	/* deal with new lines */
-<*>\r?\n							{ 
-										bool done = false;
-										do{
-											int state = _state_top("");
-
-											if(state == DEFINE_BODY)
-											{
-												finalize_define();
-											} 
-
-											done = ( state != DEFINE_BODY && state != COMMENT );
-											if(!done)
-											{
-												POP_STATE();
-											}
-
-										}while(!done);
-
-										my_location.line++;
-										my_location.col = 1;
-									}
-
-	/* catch all */
-<*>.            					{ 
-										MP(); 
-										int state = _state_top("");
-										if(state == DEFINE_BODY)
-										{
-											append_to_define_body(yytext[0]);
-										}
-										else if(state == DEFINE_ARGS
-										|| 		state == BRACKET_MATCH)
-										{
-											define_arg_push_back(yytext[0]);
-										} 
-									}				
+    /*********************************
+     * Preprocessor directives
+     **/
+<VAR_PARSE>{vWORD}                  { MP(); add_args_to_define(yytext); }
+<VAR_PARSE>"..."                    { MP(); add_args_to_define(yytext); }
+<VAR_PARSE>[\,]                     {  }
+<VAR_PARSE>[\)]                     { CHANGE_STATE(DEFINE_BODY); }
+<PARSE_DEFINE>{defineWORD}[\(]      { MP(); new_define_t(yytext); CHANGE_STATE(VAR_PARSE); }
+<PARSE_DEFINE>{defineWORD}          { MP(); new_define_t(yytext); CHANGE_STATE(DEFINE_BODY); }
+<INITIAL>"`define"                  { MP(); PUSH_STATE(PARSE_DEFINE); }
+
+<DEFINE_REMOVAL>{vWORD}             { MP(); free_define_t(yytext); POP_STATE(); }
+<INITIAL>"`undef"                   { MP(); PUSH_STATE(DEFINE_REMOVAL); }
+
+<CONDITION>{vWORD}                  { MP(); CHANGE_STATE( ((ifdef(yytext))?  INITIAL: SKIP) ); }
+<NEG_CONDITION>{vWORD}              { MP(); CHANGE_STATE( ((ifdef(yytext))?  SKIP: INITIAL) ); }
+
+    /* since the condition did not hold true, we evaluate these statement */
+<SKIP>"`elsif"                      { MP(); CHANGE_STATE(CONDITION); }
+<SKIP>"`else"                       { MP(); CHANGE_STATE(INITIAL); }
+
+    /* since the condition held true, we need to skip these */
+<INITIAL>"`elsif"                   { MP(); CHANGE_STATE(SKIP); }
+<INITIAL>"`else"                    { MP(); CHANGE_STATE(SKIP); }
+
+    /* entry point */
+<INITIAL>"`ifdef"                   { MP(); PUSH_STATE(CONDITION); }
+<INITIAL>"`ifndef"                  { MP(); PUSH_STATE(NEG_CONDITION); }
+
+    /* exit point */
+<INITIAL,SKIP>"`endif"              { MP(); POP_STATE(); }
+
+<INITIAL>"`include"                 { MP(); PUSH_STATE(INCLUDE); }
+<INCLUDE>{vSTR}                     { MP(); push_include(yytext); POP_STATE(); }
+
+<INITIAL>"`default_nettype"         { MP(); return preDEFAULT_NETTYPE;}
+<INITIAL>"`resetall"                { MP(); initialize_defaults(); }
+
+    /* unsupported commands, we skip the rest of the line */
+<INITIAL>"`timescale"               { MP(); PUSH_STATE(COMMENT); }
+<INITIAL>"`pragma"                  { MP(); PUSH_STATE(COMMENT); }
+<INITIAL>"`line"                    { MP(); PUSH_STATE(COMMENT); }
+<INITIAL>"`celldefine"              { MP(); PUSH_STATE(COMMENT); }
+<INITIAL>"`endcelldefine"           { MP(); PUSH_STATE(COMMENT); }
+<INITIAL>"`nounconnected_drive"     { MP(); PUSH_STATE(COMMENT); }
+<INITIAL>"`unconnected_drive"       { MP(); PUSH_STATE(COMMENT); }
+
+
+<INITIAL>"‘begin_keywords"          { MP(); PUSH_STATE(READ_IEEE); }
+<READ_IEEE>"\"1364-2005\""          { MP(); ieee_state.push_back(ieee_2005);            POP_STATE(); }
+<READ_IEEE>"\"1364-2001-noconfig\"" { MP(); ieee_state.push_back(ieee_2001_noconfig);    POP_STATE(); }
+<READ_IEEE>"\"1364-2001\""          { MP(); ieee_state.push_back(ieee_2001);            POP_STATE(); }
+<READ_IEEE>"\"1364-1995\""          { MP(); ieee_state.push_back(ieee_1995);            POP_STATE(); }
+<INITIAL>"`end_keywords"            { MP(); ieee_state.pop_back(); }
+
+<DEFINE_ARGS>[\)]                   { MP(); POP_STATE(); lex_string(get_complex_define().c_str()); }
+<DEFINE_ARGS>[\,]                   { MP(); next_define_arg(); }
+<BRACKET_MATCH>[\)]                 { MP(); POP_STATE(); define_arg_push_back(yytext[0]); }
+<DEFINE_ARGS,BRACKET_MATCH>[\(]     { MP(); PUSH_STATE(BRACKET_MATCH); define_arg_push_back(yytext[0]); }
+<INITIAL>[\`]{vWORD}[\(]            { MP(); load_define(yytext); PUSH_STATE(DEFINE_ARGS); }
+<INITIAL>[\`]{vWORD}                { MP(); lex_string(get_simple_define(yytext).c_str()); }
+
+    /**********************************
+     * Verilog Keywords
+     */
+
+    /*    unsupported Keywords        */
+<INITIAL>"cell"                      { MP(); return ieee_filter(vCELL); }
+<INITIAL>"config"                    { MP(); return ieee_filter(vCONFIG); }
+<INITIAL>"design"                    { MP(); return ieee_filter(vDESIGN); }
+<INITIAL>"endconfig"                 { MP(); return ieee_filter(vENDCONFIG); }
+<INITIAL>"incdir"                    { MP(); return ieee_filter(vINCDIR); }
+<INITIAL>"include"                   { MP(); return ieee_filter(vINCLUDE); }
+<INITIAL>"instance"                  { MP(); return ieee_filter(vINSTANCE); }
+<INITIAL>"liblist"                   { MP(); return ieee_filter(vLIBLIST); }
+<INITIAL>"library"                   { MP(); return ieee_filter(vLIBRARY); }
+<INITIAL>"use"                       { MP(); return ieee_filter(vUSE); }
+<INITIAL>"noshowcancelled"           { MP(); return ieee_filter(vNOSHOWCANCELLED); }
+<INITIAL>"pulsestyle_ondetect"       { MP(); return ieee_filter(vPULSESTYLE_ONDETECT); }
+<INITIAL>"pulsestyle_onevent"        { MP(); return ieee_filter(vPULSESTYLE_ONEVENT); }
+<INITIAL>"showcancelled"             { MP(); return ieee_filter(vSHOWCANCELLED); }
+<INITIAL>"casex"                     { MP(); return ieee_filter(vCASEX); }
+<INITIAL>"casez"                     { MP(); return ieee_filter(vCASEZ); }
+<INITIAL>"disable"                   { MP(); return ieee_filter(vDISABLE); }
+<INITIAL>"edge"                      { MP(); return ieee_filter(vEDGE); }
+<INITIAL>"scalared"                  { MP(); return ieee_filter(vSCALARED); }
+<INITIAL>"bufif0"                    { MP(); return ieee_filter(vBUFIF0); }
+<INITIAL>"bufif1"                    { MP(); return ieee_filter(vBUFIF1); }
+<INITIAL>"cmos"                      { MP(); return ieee_filter(vCMOS); }
+<INITIAL>"deassign"                  { MP(); return ieee_filter(vDEASSIGN); }
+<INITIAL>"endprimitive"              { MP(); return ieee_filter(vENDPRIMITIVE); }
+<INITIAL>"endtable"                  { MP(); return ieee_filter(vENDTABLE); }
+<INITIAL>"event"                     { MP(); return ieee_filter(vEVENT); }
+<INITIAL>"force"                     { MP(); return ieee_filter(vFORCE); }
+<INITIAL>"forever"                   { MP(); return ieee_filter(vFOREVER); }
+<INITIAL>"fork"                      { MP(); return ieee_filter(vFORK); }
+<INITIAL>"highz0"                    { MP(); return ieee_filter(vHIGHZ0); }
+<INITIAL>"highz1"                    { MP(); return ieee_filter(vHIGHZ1); }
+<INITIAL>"join"                      { MP(); return ieee_filter(vJOIN); }
+<INITIAL>"large"                     { MP(); return ieee_filter(vLARGE); }
+<INITIAL>"medium"                    { MP(); return ieee_filter(vMEDIUM); }
+<INITIAL>"nmos"                      { MP(); return ieee_filter(vNMOS); }
+<INITIAL>"notif0"                    { MP(); return ieee_filter(vNOTIF0); }
+<INITIAL>"notif1"                    { MP(); return ieee_filter(vNOTIF1); }
+<INITIAL>"pmos"                      { MP(); return ieee_filter(vPMOS); }
+<INITIAL>"primitive"                 { MP(); return ieee_filter(vPRIMITIVE); }
+<INITIAL>"pull0"                     { MP(); return ieee_filter(vPULL0); }
+<INITIAL>"pull1"                     { MP(); return ieee_filter(vPULL1); }
+<INITIAL>"pulldown"                  { MP(); return ieee_filter(vPULLDOWN); }
+<INITIAL>"pullup"                    { MP(); return ieee_filter(vPULLUP); }
+<INITIAL>"rcmos"                     { MP(); return ieee_filter(vRCMOS); }
+<INITIAL>"release"                   { MP(); return ieee_filter(vRELEASE); }
+<INITIAL>"repeat"                    { MP(); return ieee_filter(vREPEAT); }
+<INITIAL>"rnmos"                     { MP(); return ieee_filter(vRNMOS); }
+<INITIAL>"rpmos"                     { MP(); return ieee_filter(vRPMOS); }
+<INITIAL>"rtran"                     { MP(); return ieee_filter(vRTRAN); }
+<INITIAL>"rtranif0"                  { MP(); return ieee_filter(vRTRANIF0); }
+<INITIAL>"rtranif1"                  { MP(); return ieee_filter(vRTRANIF1); }
+<INITIAL>"small"                     { MP(); return ieee_filter(vSMALL); }
+<INITIAL>"strong0"                   { MP(); return ieee_filter(vSTRONG0); }
+<INITIAL>"strong1"                   { MP(); return ieee_filter(vSTRONG1); }
+<INITIAL>"supply0"                   { MP(); return ieee_filter(vSUPPLY0); }
+<INITIAL>"supply1"                   { MP(); return ieee_filter(vSUPPLY1); }
+<INITIAL>"table"                     { MP(); return ieee_filter(vTABLE); }
+<INITIAL>"time"                      { MP(); return ieee_filter(vTIME); }
+<INITIAL>"tran"                      { MP(); return ieee_filter(vTRAN); }
+<INITIAL>"tranif0"                   { MP(); return ieee_filter(vTRANIF0); }
+<INITIAL>"tranif1"                   { MP(); return ieee_filter(vTRANIF1); }
+<INITIAL>"vectored"                  { MP(); return ieee_filter(vVECTORED); }
+<INITIAL>"wait"                      { MP(); return ieee_filter(vWAIT); }
+<INITIAL>"weak0"                     { MP(); return ieee_filter(vWEAK0); }
+<INITIAL>"weak1"                     { MP(); return ieee_filter(vWEAK1); }
+
+    /* Begin Scoped items */
+<INITIAL>"begin"                     { MP(); push_scope(); return ieee_filter(vBEGIN); }
+<INITIAL>"function"                  { MP(); push_scope(); return ieee_filter(vFUNCTION); }
+<INITIAL>"module"                    { MP(); push_scope(); return ieee_filter(vMODULE); }
+<INITIAL>"macromodule"               { MP(); push_scope(); return ieee_filter(vMODULE); }
+<INITIAL>"task"                      { MP(); push_scope(); return ieee_filter(vTASK); }
+
+    /* End Scoped items */
+<INITIAL>"end"                       { MP(); return ieee_filter(vEND); }
+<INITIAL>"endfunction"               { MP(); return ieee_filter(vENDFUNCTION); }
+<INITIAL>"endmodule"                 { MP(); return ieee_filter(vENDMODULE); }
+<INITIAL>"endtask"                   { MP(); return ieee_filter(vENDTASK); }
+
+    /*    Keywords    */
+<INITIAL>"always"                    { MP(); return ieee_filter(vALWAYS); }
+<INITIAL>"and"                       { MP(); return ieee_filter(vAND); }
+<INITIAL>"assign"                    { MP(); return ieee_filter(vASSIGN); }
+<INITIAL>"automatic"                 { MP(); return ieee_filter(vAUTOMATIC); }
+<INITIAL>"case"                      { MP(); return ieee_filter(vCASE); }
+<INITIAL>"default"                   { MP(); return ieee_filter(vDEFAULT); }
+<INITIAL>"defparam"                  { MP(); return ieee_filter(vDEFPARAM); }
+<INITIAL>"else"                      { MP(); return ieee_filter(vELSE); }
+<INITIAL>"endcase"                   { MP(); return ieee_filter(vENDCASE); }
+<INITIAL>"endspecify"                { MP(); return ieee_filter(vENDSPECIFY); }
+<INITIAL>"endgenerate"               { MP(); return ieee_filter(vENDGENERATE); }
+<INITIAL>"for"                       { MP(); return ieee_filter(vFOR); }
+<INITIAL>"if"                        { MP(); return ieee_filter(vIF); }
+<INITIAL>"initial"                   { MP(); return ieee_filter(vINITIAL); }
+<INITIAL>"inout"                     { MP(); return ieee_filter(vINOUT); }
+<INITIAL>"input"                     { MP(); return ieee_filter(vINPUT); }
+<INITIAL>"integer"                   { MP(); return ieee_filter(vINTEGER); }
+<INITIAL>"generate"                  { MP(); return ieee_filter(vGENERATE); }
+<INITIAL>"genvar"                    { MP(); return ieee_filter(vGENVAR); }
+<INITIAL>"nand"                      { MP(); return ieee_filter(vNAND); }
+<INITIAL>"negedge"                   { MP(); return ieee_filter(vNEGEDGE); }
+<INITIAL>"nor"                       { MP(); return ieee_filter(vNOR); }
+<INITIAL>"not"                       { MP(); return ieee_filter(vNOT); }
+<INITIAL>"or"                        { MP(); return ieee_filter(vOR); }
+<INITIAL>"output"                    { MP(); return ieee_filter(vOUTPUT); }
+<INITIAL>"parameter"                 { MP(); return ieee_filter(vPARAMETER); }
+<INITIAL>"localparam"                { MP(); return ieee_filter(vLOCALPARAM); }
+<INITIAL>"posedge"                   { MP(); return ieee_filter(vPOSEDGE); }
+<INITIAL>"signed"                    { MP(); return ieee_filter(vSIGNED); }
+<INITIAL>"unsigned"                  { MP(); return ieee_filter(vUNSIGNED); }
+<INITIAL>"specify"                   { MP(); return ieee_filter(vSPECIFY); }
+<INITIAL>"while"                     { MP(); return ieee_filter(vWHILE); }
+<INITIAL>"xnor"                      { MP(); return ieee_filter(vXNOR); }
+<INITIAL>"xor"                       { MP(); return ieee_filter(vXOR); }
+<INITIAL>"specparam"                 { MP(); return ieee_filter(vSPECPARAM); }
+<INITIAL>"buf"                       { MP(); return ieee_filter(vBUF); }
+
+    /* Net types */
+<INITIAL>"wire"                      { MP(); return ieee_filter(vWIRE); }
+<INITIAL>"tri"                       { MP(); return ieee_filter(vTRI); }
+<INITIAL>"tri0"                      { MP(); return ieee_filter(vTRI0); }
+<INITIAL>"tri1"                      { MP(); return ieee_filter(vTRI1); }
+<INITIAL>"wand"                      { MP(); return ieee_filter(vWAND); }
+<INITIAL>"wor"                       { MP(); return ieee_filter(vWOR); }
+<INITIAL>"triand"                    { MP(); return ieee_filter(vTRIAND); }
+<INITIAL>"trior"                     { MP(); return ieee_filter(vTRIOR); }
+<INITIAL>"trireg"                    { MP(); return ieee_filter(vTRIREG); }
+<INITIAL>"uwire"                     { MP(); return ieee_filter(vUWIRE); }
+<INITIAL>"uwire"                     { MP(); return ieee_filter(vUWIRE); }
+<INITIAL>"none"                      { MP(); return ieee_filter(vNONE); }
+<INITIAL>"reg"                       { MP(); return ieee_filter(vREG); }
+
+    /**********************************
+     * Verilog Operators (vo)
+     */
+<INITIAL>"&&&"                       { MP(); return ieee_filter(voANDANDAND); }
+<INITIAL>"**"                        { MP(); return ieee_filter(voPOWER); }
+<INITIAL>"&&"                        { MP(); return ieee_filter(voANDAND); }
+<INITIAL>"||"                        { MP(); return ieee_filter(voOROR); }
+<INITIAL>"<="                        { MP(); return ieee_filter(voLTE); }
+<INITIAL>"=>"                        { MP(); return ieee_filter(voEGT); }
+<INITIAL>">="                        { MP(); return ieee_filter(voGTE); }
+<INITIAL>"<<"                        { MP(); return ieee_filter(voSLEFT); }
+<INITIAL>"<<<"                       { MP(); return ieee_filter(voASLEFT); }
+<INITIAL>">>"                        { MP(); return ieee_filter(voSRIGHT); }
+<INITIAL>">>>"                       { MP(); return ieee_filter(voASRIGHT); }
+<INITIAL>"=="                        { MP(); return ieee_filter(voEQUAL); }
+<INITIAL>"!="                        { MP(); return ieee_filter(voNOTEQUAL); }
+<INITIAL>"==="                       { MP(); return ieee_filter(voCASEEQUAL); }
+<INITIAL>"!=="                       { MP(); return ieee_filter(voCASENOTEQUAL); }
+<INITIAL>"^~"                        { MP(); return ieee_filter(voXNOR); }
+<INITIAL>"~^"                        { MP(); return ieee_filter(voXNOR); }
+<INITIAL>"~&"                        { MP(); return ieee_filter(voNAND); }
+<INITIAL>"~|"                        { MP(); return ieee_filter(voNOR); }
+<INITIAL>"+:"                        { MP(); return ieee_filter(voPLUSCOLON); }
+<INITIAL>"-:"                        { MP(); return ieee_filter(voMINUSCOLON); }
+
+    /**********************************
+     * Verilog System (vs) Functions
+     */
+<INITIAL>"$clog2"                    { MP(); return ieee_filter(vsCLOG2); }
+<INITIAL>"$unsigned"                 { MP(); return ieee_filter(vsUNSIGNED); }
+<INITIAL>"$signed"                   { MP(); return ieee_filter(vsSIGNED); }
+<INITIAL>"$finish"                   { MP(); return ieee_filter(vsFINISH); }
+<INITIAL>"$display"                  { MP(); return ieee_filter(vsDISPLAY); }
+    /* catch all C functions */
+<INITIAL>[\$]{vWORD}                 { MP(); return ieee_filter(vsFUNCTION); }
+
+    /* Integers */
+<INITIAL>{vINT}                      { MP(); yylval.num_value = vtr::strdup(yytext); return vINT_NUMBER; }
+    /* Strings */
+<INITIAL>{vSTR}                      { MP(); yylval.num_value = vtr::strdup(yytext); return vSTRING; }
+    /* Numbers */
+<INITIAL>[[:digit:]]*'[sS]?{vBIN}    { MP(); yylval.num_value = vtr::strdup(yytext); return vNUMBER; }
+<INITIAL>[[:digit:]]*'[sS]?{vHEX}    { MP(); yylval.num_value = vtr::strdup(yytext); return vNUMBER; }
+<INITIAL>[[:digit:]]*'[sS]?{vOCT}    { MP(); yylval.num_value = vtr::strdup(yytext); return vNUMBER; }
+<INITIAL>[[:digit:]]*'[sS]?{vDEC}    { MP(); yylval.num_value = vtr::strdup(yytext); return vNUMBER; }
+
+    /*    operands    */
+<INITIAL>{vWORD}(\.{vWORD})*         { MP(); yylval.id_name = vtr::strdup(yytext); return vSYMBOL_ID; }
+
+    /* return operators */
+<INITIAL>{vPUNCT}                    { MP(); return yytext[0]; }
+
+    /************
+     * general stuff 
+     **/
+
+    /* single line comment */
+<*>[\/][\/]                         { 
+                                        int state = TOP_STATE();
+                                        if (state == DEFINE_BODY)
+                                        {
+                                            /**
+                                            * single line comments will automaticaly continue on if we
+                                            * escape the new line, to prevent issues, we stop processing the macro body
+                                            */
+                                            finalize_define();
+                                            POP_STATE();
+                                        }
+                                        if(state != COMMENT
+                                        && state != MULTI_LINE_COMMENT)
+                                        {
+                                            PUSH_STATE(COMMENT);
+                                        }
+                                    }
+    /* multi line comment */
+<*>[\/][\*]                         { 
+                                        int state = TOP_STATE();
+                                        if(state != COMMENT
+                                        && state != MULTI_LINE_COMMENT)
+                                        {
+                                            PUSH_STATE(MULTI_LINE_COMMENT);
+                                        }
+                                    }
+
+<MULTI_LINE_COMMENT>[\*][\/]        { POP_STATE(); }
+
+<*>[[:blank:]]+                     {    
+                                        int state = TOP_STATE();
+                                        if(state == DEFINE_BODY)
+                                        {
+                                            append_to_define_body(' ');
+                                        }
+                                        else if(state == DEFINE_ARGS
+                                        ||        state == BRACKET_MATCH)
+                                        {
+                                            define_arg_push_back(yytext[0]);
+                                        } 
+                                    }
+
+<*><<EOF>>                            { if ( ! pop_include() ){ free_define_map(); yyterminate(); } }
+
+    /* skip escapped newline */
+<*>\\\r?\n                            { my_location.line++; my_location.col = 1; }
+
+    /* deal with new lines */
+<*>\r?\n                            { 
+                                        bool done = false;
+                                        do{
+                                            int state = TOP_STATE();
+
+                                            if(state == DEFINE_BODY)
+                                            {
+                                                finalize_define();
+                                            } 
+
+                                            done = ( state != DEFINE_BODY && state != COMMENT );
+                                            if(!done)
+                                            {
+                                                POP_STATE();
+                                            }
+
+                                        }while(!done);
+
+                                        my_location.line++;
+                                        my_location.col = 1;
+                                    }
+
+    /* catch all */
+<*>.                                { 
+                                        MP(); 
+                                        int state = TOP_STATE();
+                                        if(state == DEFINE_BODY)
+                                        {
+                                            append_to_define_body(yytext[0]);
+                                        }
+                                        else if(state == DEFINE_ARGS
+                                        ||        state == BRACKET_MATCH)
+                                        {
+                                            define_arg_push_back(yytext[0]);
+                                        } 
+                                        else if(state == READ_IEEE)
+                                        {
+                                            /* catch stuck parser */
+                                            POP_STATE();
+                                        }
+                                    }                
 
 %%
 
-void MP()		
+void MP()        
 { 
-	if (configuration.print_parse_tokens) 
-	{
-		printf("%d %s\n", my_location.line, yytext);
-	} 
+    if (configuration.print_parse_tokens) 
+    {
+        printf("%d %s\n", my_location.line, yytext);
+    } 
 }
 
-int _state_top(const char *str)		
+int top_flex_state(const char *str)        
 { 
-	int state = state_stack.back(); 
-	if (configuration.print_parse_tokens && strlen(str)) 
-	{
-		printf("%s state: %s\n", str,
-			(state == INCLUDE)? 			"INCLUDE":
-			(state == COMMENT)? 			"COMMENT":
-			(state == MULTI_LINE_COMMENT)? 	"MULTI_LINE_COMMENT":
-			(state == DEFINE_BODY)? 		"DEFINE_BODY":
-			(state == SKIP)? 				"SKIP":
-			(state == ELIFCONDITION)? 		"ELIFCONDITION":
-			(state == NEG_CONDITION)? 		"NEG_CONDITION":
-			(state == CONDITION)? 			"CONDITION":
-			(state == DEFINE_REMOVAL)? 		"DEFINE_REMOVAL":
-			(state == VAR_PARSE)? 			"VAR_PARSE":
-			(state == PARSE_DEFINE)? 		"PARSE_DEFINE":
-			(state == DEFINE_ARGS)? 		"DEFINE_ARGS":
-											"INITIAL"
-		);
-	} 
-	return state;
-}
-
-void _pop_state()		
-{ 
-	state_stack.pop_back(); 
-	if(state_stack.empty())
-	{
-		state_stack.push_back(INITIAL);
-	} 
-}
-
-void _push_state(int state)	
-{ 
-	state_stack.push_back(state); 
+    if(flex_state.empty())
+    {
+        flex_state.push_back(INITIAL);
+    } 
+    int state = flex_state.back(); 
+    if (configuration.print_parse_tokens && strlen(str)) 
+    {
+        printf("%s state: %s\n", str,
+            (state == INCLUDE)?            "INCLUDE":
+            (state == COMMENT)?            "COMMENT":
+            (state == MULTI_LINE_COMMENT)?    "MULTI_LINE_COMMENT":
+            (state == DEFINE_BODY)?        "DEFINE_BODY":
+            (state == SKIP)?                "SKIP":
+            (state == ELIFCONDITION)?        "ELIFCONDITION":
+            (state == NEG_CONDITION)?        "NEG_CONDITION":
+            (state == CONDITION)?            "CONDITION":
+            (state == DEFINE_REMOVAL)?        "DEFINE_REMOVAL":
+            (state == VAR_PARSE)?            "VAR_PARSE":
+            (state == PARSE_DEFINE)?        "PARSE_DEFINE":
+            (state == DEFINE_ARGS)?        "DEFINE_ARGS":
+                                            "INITIAL"
+        );
+    } 
+    return state;
 }
 
 static bool has_current_parse_file()
 {
-	return (
-		my_location.file < include_file_names.size()
-		&& my_location.file >= 0
-	);
+    return (
+        my_location.file < include_file_names.size()
+        && my_location.file >= 0
+    );
 }
 
 void lex_string(const char * str)
 {
 
-	if (configuration.print_parse_tokens) 
-	{
-		printf("Processing define %s\n", str);
-	} 
-
-	if(has_current_parse_file() 
-	&& current_include_stack.back() == my_location.file)
-	{
-	 	include_file_names[my_location.file].second = my_location.line;
-	}
-
-	/* check current depth, prevent too much macro recursion */
-	loc_t posible_error_location = {include_file_names[my_location.file].second, my_location.file, -1};
-	if(current_include_stack.size() > RECURSIVE_LIMIT)
-	{
-		error_message(PARSER, posible_error_location,
-			"Reached upper macro recursion limit of %d", 
-			RECURSIVE_LIMIT);
-	}
-	else if(current_include_stack.size() > (RECURSIVE_LIMIT/2))
-	{
-		warning_message(PARSER, posible_error_location,
-			"Reached halfway to upper macro recursion limit of %d", 
-			RECURSIVE_LIMIT);
-	}
-
-
-	current_include_stack.push_back(-1);
-	my_location.line = 0;
-
-	YY_BUFFER_STATE cur = YY_CURRENT_BUFFER;
-	YY_BUFFER_STATE yybuff = yy_scan_string(str);
-	yy_switch_to_buffer(cur);
-	yypush_buffer_state(yybuff);
+    if (configuration.print_parse_tokens) 
+    {
+        printf("Processing define %s\n", str);
+    } 
+
+    if(has_current_parse_file() 
+    && current_include_stack.back() == my_location.file)
+    {
+        include_file_names[my_location.file].second = my_location.line;
+    }
+
+    /* check current depth, prevent too much macro recursion */
+    loc_t posible_error_location = {include_file_names[my_location.file].second, my_location.file, -1};
+    if(current_include_stack.size() > RECURSIVE_LIMIT)
+    {
+        error_message(PARSER, posible_error_location,
+            "Reached upper macro recursion limit of %d", 
+            RECURSIVE_LIMIT);
+    }
+    else if(current_include_stack.size() > (RECURSIVE_LIMIT/2))
+    {
+        warning_message(PARSER, posible_error_location,
+            "Reached halfway to upper macro recursion limit of %d", 
+            RECURSIVE_LIMIT);
+    }
+
+
+    current_include_stack.push_back(-1);
+    my_location.line = 0;
+
+    YY_BUFFER_STATE cur = YY_CURRENT_BUFFER;
+    YY_BUFFER_STATE yybuff = yy_scan_string(str);
+    yy_switch_to_buffer(cur);
+    yypush_buffer_state(yybuff);
 
 }
 
 void push_include(const char *file_name)
 {
 
-	printf("Adding file %s to parse list\n", file_name);
-
-	std::string tmp(file_name);
-
-	if(tmp[0] == '"')
-	{
-		tmp.erase(0,1);
-	}
-
-	if(tmp.back() == '"')
-	{
-		tmp.pop_back();
-	}
-
-	std::string current_file = "";
-	if(has_current_parse_file())
-	{
-		current_file = include_file_names[my_location.file].first;
-		if(current_include_stack.back() == my_location.file)
-		{
-	 		include_file_names[my_location.file].second = my_location.line;
-		}
-	}
-
-	/* we add the path from the current file */
-	size_t loc = current_file.find_last_of("/");
-	if(loc == std::string::npos)
-	{
-		current_file = tmp;
-	}
-	else
-	{
-		current_file = current_file.substr(0, loc + 1) + tmp;
-	}
-
-	yyin = fopen(current_file.c_str(), "r");
-	if(yyin == NULL)
-	{
-		printf("Unable to open %s, trying %s\n", current_file.c_str(), tmp.c_str());
-		current_file = tmp;
-		yyin = open_file(current_file.c_str(), "r");
-	}
-	
-	my_location.line = 0;
-	current_include_stack.push_back(include_file_names.size());
-	include_file_names.push_back({current_file,my_location.line});
-
-	my_location.file = current_include_stack.back();
-	assert_supported_file_extension(include_file_names.back().first.c_str() , my_location); 
-
-	YY_BUFFER_STATE yybuff = yy_create_buffer( yyin, YY_BUF_SIZE );
-	yypush_buffer_state(yybuff);
+    printf("Adding file %s to parse list\n", file_name);
+
+    std::string tmp(file_name);
+
+    if(tmp[0] == '"')
+    {
+        tmp.erase(0,1);
+    }
+
+    if(tmp.back() == '"')
+    {
+        tmp.pop_back();
+    }
+
+    std::string current_file = "";
+    if(has_current_parse_file())
+    {
+        current_file = include_file_names[my_location.file].first;
+        if(current_include_stack.back() == my_location.file)
+        {
+            include_file_names[my_location.file].second = my_location.line;
+        }
+    }
+
+    /* we add the path from the current file */
+    size_t loc = current_file.find_last_of("/");
+    if(loc == std::string::npos)
+    {
+        current_file = tmp;
+    }
+    else
+    {
+        current_file = current_file.substr(0, loc + 1) + tmp;
+    }
+
+    yyin = fopen(current_file.c_str(), "r");
+    if(yyin == NULL)
+    {
+        printf("Unable to open %s, trying %s\n", current_file.c_str(), tmp.c_str());
+        current_file = tmp;
+        yyin = open_file(current_file.c_str(), "r");
+    }
+    
+    my_location.line = 0;
+    current_include_stack.push_back(include_file_names.size());
+    include_file_names.push_back({current_file,my_location.line});
+
+    my_location.file = current_include_stack.back();
+    assert_supported_file_extension(include_file_names.back().first.c_str() , my_location); 
+
+    YY_BUFFER_STATE yybuff = yy_create_buffer( yyin, YY_BUF_SIZE );
+    yypush_buffer_state(yybuff);
 
 }
 
 bool pop_include()
 {
-	if(has_current_parse_file())
-	{
-		if(configuration.print_parse_tokens)
-		{
-			printf("Poping file %s from parse list\n", include_file_names[my_location.file].first.c_str());
-		}
-		
-		if(yyin)
-		{
-			fflush(yyin);
-			fclose(yyin);
-			yyin = NULL;
-		}
-	}
-
-	if(!current_include_stack.empty())
-	{
-		current_include_stack.pop_back();
-	}
-
-	if(!current_include_stack.empty())
-	{
-		if(current_include_stack.back() != -1)
-		{
-			my_location.file = current_include_stack.back();
-		}
-	}
-	else
-	{
-		my_location.file = -1;
-	}
-
-	if(has_current_parse_file() && my_location.file >= 0)
-	{
-		my_location.line = include_file_names[my_location.file].second;
-
-		if(configuration.print_parse_tokens)
-		{
-			printf("Reading file %s from line %d\n", include_file_names[my_location.file].first.c_str(), my_location.line);
-		}
-	}
-	else
-	{
-		my_location.line = -1;
-	}
-	
-	yypop_buffer_state(); 
-	return ( YY_CURRENT_BUFFER );
+    if(has_current_parse_file())
+    {
+        if(configuration.print_parse_tokens)
+        {
+            printf("Poping file %s from parse list\n", include_file_names[my_location.file].first.c_str());
+        }
+        
+        if(yyin)
+        {
+            fflush(yyin);
+            fclose(yyin);
+            yyin = NULL;
+        }
+    }
+
+    if(!current_include_stack.empty())
+    {
+        current_include_stack.pop_back();
+    }
+
+    if(!current_include_stack.empty())
+    {
+        if(current_include_stack.back() != -1)
+        {
+            my_location.file = current_include_stack.back();
+        }
+    }
+    else
+    {
+        my_location.file = -1;
+    }
+
+    if(has_current_parse_file() && my_location.file >= 0)
+    {
+        my_location.line = include_file_names[my_location.file].second;
+
+        if(configuration.print_parse_tokens)
+        {
+            printf("Reading file %s from line %d\n", include_file_names[my_location.file].first.c_str(), my_location.line);
+        }
+    }
+    else
+    {
+        my_location.line = -1;
+    }
+    
+    yypop_buffer_state(); 
+    return ( YY_CURRENT_BUFFER );
 }
 
 void initialize_defaults()
 {
-	default_net_type = WIRE;
-	current_define = NULL;
-	free_define_map();
+    default_net_type = WIRE;
+    ieee_state.clear();
+    current_define = NULL;
+    free_define_map();
 }
 
 void new_define_t(const char* id)
 {
-	std::string tmp(id);
-	if(tmp.back() == '(')
-	{
-		tmp.pop_back();
-	}
-
-	defines_t *new_define = new defines_t();
-	new_define->name = tmp;
-	new_define->use_va_args = false;
-	new_define->args = std::vector<std::string>();
-	new_define->body = "";
-	
-	if(defines_map.find(tmp) != defines_map.end())
-	{
-		warning_message(PARSER, my_location, "%s is redefined, overwritting its value", id);
-		delete defines_map[tmp];	
-	}
-
-	defines_map[tmp] = new_define;
-	current_define = new_define;
+    std::string tmp(id);
+    if(tmp.back() == '(')
+    {
+        tmp.pop_back();
+    }
+
+    defines_t *new_define = new defines_t();
+    new_define->name = tmp;
+    new_define->use_va_args = false;
+    new_define->args = std::vector<std::string>();
+    new_define->body = "";
+    
+    if(defines_map.find(tmp) != defines_map.end())
+    {
+        warning_message(PARSER, my_location, "%s is redefined, overwritting its value", id);
+        delete defines_map[tmp];    
+    }
+
+    defines_map[tmp] = new_define;
+    current_define = new_define;
 }
 
 void free_define_t(const char *id)
 {
-	std::string tmp(id);
-	if(defines_map.find(tmp) != defines_map.end())
-	{
-		delete defines_map[tmp];
-		defines_map.erase(tmp);
-	}
+    std::string tmp(id);
+    if(defines_map.find(tmp) != defines_map.end())
+    {
+        delete defines_map[tmp];
+        defines_map.erase(tmp);
+    }
 }
 
 void free_define_map()
 {
-	for(auto kv: defines_map)
-	{
-		delete kv.second;
-	}
+    for(auto kv: defines_map)
+    {
+        delete kv.second;
+    }
 }
 
 std::string get_simple_define(const char *str)
 {
-	load_define(str);
-	return get_complex_define();
+    load_define(str);
+    return get_complex_define();
 }
 
 std::string get_complex_define()
 {
-	if(current_define)
-	{
-		std::string va_args_replacement = "";
-
-		if( current_args.size() < current_define->args.size())
-		{
-			error_message(PARSER, my_location, 
-				"define `%s is being used with too few arguments, Expected %ld, got %ld", 
-					current_define->name.c_str(), current_define->args.size(),current_args.size());
-		}
-		else if( current_args.size() > current_define->args.size())
-		{
-			if(! current_define->use_va_args) {
-				error_message(PARSER, my_location, 
-					"define `%s is being used with too many arguments, Expected %ld, got %ld", 
-						current_define->name.c_str(), current_define->args.size(),current_args.size());
-			} else {
-				while(current_define->args.size() != current_args.size())
-				{
-					if(va_args_replacement != "")
-					{
-						va_args_replacement = ", " + va_args_replacement;
-					}
-					va_args_replacement = current_args.back() + va_args_replacement;
-					current_args.pop_back();
-				}
-
-			}
-		}
-
-		if (current_define->use_va_args)
-		{
-			current_define->args.push_back("__VA_ARGS__");
-			current_args.push_back(va_args_replacement);
-		}
-
-
-		for(int i=0; i<current_define->args.size(); i++)
-		{
-			std::string original_arg = current_define->args[i];
-			std::string replacement_arg = current_args[i];
-
-			size_t pos = current_define_body.find( original_arg, 0 );
-			while ( pos != std::string::npos )
-			{
-				current_define_body.erase(pos, original_arg.size());
-				current_define_body.insert( pos, replacement_arg );
-				pos += replacement_arg.size();
-				pos = current_define_body.find( original_arg, pos );
-			}
-		}
-
-		if(configuration.print_parse_tokens )
-		{
-			printf("DEFINE = %s\n",  current_define_body.c_str());
-		}
-	}
-	return current_define_body;
+    if(current_define)
+    {
+        std::string va_args_replacement = "";
+
+        if( current_args.size() < current_define->args.size())
+        {
+            error_message(PARSER, my_location, 
+                "define `%s is being used with too few arguments, Expected %ld, got %ld", 
+                    current_define->name.c_str(), current_define->args.size(),current_args.size());
+        }
+        else if( current_args.size() > current_define->args.size())
+        {
+            if(! current_define->use_va_args) {
+                error_message(PARSER, my_location, 
+                    "define `%s is being used with too many arguments, Expected %ld, got %ld", 
+                        current_define->name.c_str(), current_define->args.size(),current_args.size());
+            } else {
+                while(current_define->args.size() != current_args.size())
+                {
+                    if(va_args_replacement != "")
+                    {
+                        va_args_replacement = ", " + va_args_replacement;
+                    }
+                    va_args_replacement = current_args.back() + va_args_replacement;
+                    current_args.pop_back();
+                }
+
+            }
+        }
+
+        if (current_define->use_va_args)
+        {
+            current_define->args.push_back("__VA_ARGS__");
+            current_args.push_back(va_args_replacement);
+        }
+
+
+        for(int i=0; i<current_define->args.size(); i++)
+        {
+            std::string original_arg = current_define->args[i];
+            std::string replacement_arg = current_args[i];
+
+            size_t pos = current_define_body.find( original_arg, 0 );
+            while ( pos != std::string::npos )
+            {
+                current_define_body.erase(pos, original_arg.size());
+                current_define_body.insert( pos, replacement_arg );
+                pos += replacement_arg.size();
+                pos = current_define_body.find( original_arg, pos );
+            }
+        }
+
+        if(configuration.print_parse_tokens )
+        {
+            printf("DEFINE = %s\n",  current_define_body.c_str());
+        }
+    }
+    return current_define_body;
 }
 
 void next_define_arg()
 {
-	current_args.push_back("");
+    current_args.push_back("");
 }
 
 void define_arg_push_back(char c)
 {
-	if(current_args.empty())
-	{
-		next_define_arg();
-	}
+    if(current_args.empty())
+    {
+        next_define_arg();
+    }
 
-	current_args.back().push_back(c);
+    current_args.back().push_back(c);
 }
 
 void load_define(const char *str)
 {
-	std::string tmp(str);
-
-	current_define = NULL;
-	current_define_body = "";
-	current_args = std::vector<std::string>();
-
-	// compiler specific macros
-	if(tmp == "`__LINE__") 
-	{
-		current_define_body = std::to_string(my_location.line + 1 /* 0 indexed */);
-	}
-	else if (tmp == "`__FILE__")
-	{
-		current_define_body = "\"" + std::string(configuration.list_of_file_names[my_location.file]) + "\"";
-	}
-	else
-	{
-		if(tmp[0] == '`')
-		{
-			tmp.erase(0,1);
-		}
-
-		if(tmp.back() == '(')
-		{
-			tmp.pop_back();
-		}
-
-		auto itter = defines_map.find(tmp);
-		if(itter == defines_map.end())
-		{
-			if(tmp == "elif")
-			{
-				warning_message(PARSER, my_location, 
-					"%s", "using `elif, when you probably meant `elsif");
-			}
-			else
-			{
-				warning_message(PARSER, my_location, 
-					"%s define cannot be found, replacing with empty string and continuing synthesis", 
-					tmp.c_str());
-			}
-		}
-		else
-		{
-			current_define = itter->second;
-			current_define_body = current_define->body;
-		}
-	}
+    std::string tmp(str);
+
+    current_define = NULL;
+    current_define_body = "";
+    current_args = std::vector<std::string>();
+
+    // compiler specific macros
+    if(tmp == "`__LINE__") 
+    {
+        current_define_body = std::to_string(my_location.line + 1 /* 0 indexed */);
+    }
+    else if (tmp == "`__FILE__")
+    {
+        current_define_body = "\"" + std::string(configuration.list_of_file_names[my_location.file]) + "\"";
+    }
+    else
+    {
+        if(tmp[0] == '`')
+        {
+            tmp.erase(0,1);
+        }
+
+        if(tmp.back() == '(')
+        {
+            tmp.pop_back();
+        }
+
+        auto itter = defines_map.find(tmp);
+        if(itter == defines_map.end())
+        {
+            if(tmp == "elif")
+            {
+                warning_message(PARSER, my_location, 
+                    "%s", "using `elif, when you probably meant `elsif");
+            }
+            else
+            {
+                warning_message(PARSER, my_location, 
+                    "%s define cannot be found, replacing with empty string and continuing synthesis", 
+                    tmp.c_str());
+            }
+        }
+        else
+        {
+            current_define = itter->second;
+            current_define_body = current_define->body;
+        }
+    }
 }
 
 void append_to_define_body(char c)
 {
-	current_define->body.push_back(c);
+    current_define->body.push_back(c);
 }
 
 void add_args_to_define(const char* str)
 {
-	std::string tmp(str);
-	if(current_define->use_va_args)
-	{
-		error_message(PARSER, my_location, 
-				"%s","... must be used as the last argument of a `define");
-	}
-	else if(tmp == "...")
-	{
-		current_define->use_va_args = true;
-	}
-	else
-	{
-		for(int i=0; i < current_define->args.size(); i++)
-		{
-			if(tmp == current_define->args[i])
-			{
-				error_message(PARSER, my_location, 
-					"%s","define has two argument with same name");
-			}
-		}
-
-		current_define->args.push_back(std::string(str));
-	}
+    std::string tmp(str);
+    if(current_define->use_va_args)
+    {
+        error_message(PARSER, my_location, 
+                "%s","... must be used as the last argument of a `define");
+    }
+    else if(tmp == "...")
+    {
+        current_define->use_va_args = true;
+    }
+    else
+    {
+        for(int i=0; i < current_define->args.size(); i++)
+        {
+            if(tmp == current_define->args[i])
+            {
+                error_message(PARSER, my_location, 
+                    "%s","define has two argument with same name");
+            }
+        }
+
+        current_define->args.push_back(std::string(str));
+    }
 }
 
 void finalize_define()
 {
-	current_define = NULL;
+    current_define = NULL;
 }
 
 bool ifdef(const char* id)
 {
-	return ( defines_map.find(std::string(id)) != defines_map.end() );
+    return ( defines_map.find(std::string(id)) != defines_map.end() );
 }
+
+int ieee_filter(int return_type)
+{
+    extern int ieee_filter(int std_version, int ret);
+    
+    if(ieee_state.empty())
+    {
+        ieee_state.push_back(ieee_2005);
+    } 
+    int std_version = ieee_state.back(); 
+    if (configuration.print_parse_tokens) 
+    {
+        printf("ieee version used: %s\n", ieee_std_STR[std_version]);
+    } 
+    
+    return ieee_filter(std_version, return_type);
+}
\ No newline at end of file
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/automatic/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/keywords/automatic/synthesis_result.json
index 28b36a10a0e..4627b561c5c 100644
--- a/ODIN_II/regression_test/benchmark/task/keywords/automatic/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/keywords/automatic/synthesis_result.json
@@ -7,8 +7,8 @@
             "NETLIST recursive_function.v:8 This output (simple_op.function_instance_0.function_instance_1^factorial~0) must exist...must be an error"
         ],
         "warnings": [
-            "AST recursive_function.v:14 ODIN II does not (yet) differentiate between automatic and static tasks & functions.IGNORING",
-            "AST recursive_function.v:14 ODIN_II does not fully support input/output integers in functions"
+            "AST recursive_function.v:8 Odin does not handle signed REG (factorial)",
+            "AST recursive_function.v:14 ODIN II does not (yet) differentiate between automatic and static tasks & functions.IGNORING"
         ]
     },
     "automatic/recursive_task/no_arch": {
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/for/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/keywords/for/synthesis_result.json
index 9c4da843dce..e092ac8686c 100644
--- a/ODIN_II/regression_test/benchmark/task/keywords/for/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/keywords/for/synthesis_result.json
@@ -2,6 +2,9 @@
     "for/generate_for_int/no_arch": {
         "test_name": "for/generate_for_int/no_arch",
         "verilog": "generate_for_int.v",
+        "warnings": [
+            "AST generate_for.vh:6 Odin does not handle signed GENVAR (i)"
+        ],
         "max_rss(MiB)": 19.3,
         "exec_time(ms)": 14.4,
         "synthesis_time(ms)": 12.9,
@@ -12,6 +15,9 @@
     "for/generate_for_ultra_wide/no_arch": {
         "test_name": "for/generate_for_ultra_wide/no_arch",
         "verilog": "generate_for_ultra_wide.v",
+        "warnings": [
+            "AST generate_for.vh:6 Odin does not handle signed GENVAR (i)"
+        ],
         "max_rss(MiB)": 1521.5,
         "exec_time(ms)": 7026.5,
         "synthesis_time(ms)": 7025.1,
@@ -22,6 +28,9 @@
     "for/generate_for_wide/no_arch": {
         "test_name": "for/generate_for_wide/no_arch",
         "verilog": "generate_for_wide.v",
+        "warnings": [
+            "AST generate_for.vh:6 Odin does not handle signed GENVAR (i)"
+        ],
         "max_rss(MiB)": 11.9,
         "exec_time(ms)": 3.8,
         "synthesis_time(ms)": 2.2,
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/genvar/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/keywords/genvar/synthesis_result.json
index e48759c141a..28b5467dc2f 100644
--- a/ODIN_II/regression_test/benchmark/task/keywords/genvar/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/keywords/genvar/synthesis_result.json
@@ -2,6 +2,9 @@
     "genvar/generate_for/no_arch": {
         "test_name": "genvar/generate_for/no_arch",
         "verilog": "generate_for.v",
+        "warnings": [
+            "AST generate_for.v:7 Odin does not handle signed GENVAR (i)"
+        ],
         "max_rss(MiB)": 12.3,
         "exec_time(ms)": 2.6,
         "synthesis_time(ms)": 1.5,
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/input/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/input/simulation_result.json
new file mode 100644
index 00000000000..9170abbd23c
--- /dev/null
+++ b/ODIN_II/regression_test/benchmark/task/keywords/input/simulation_result.json
@@ -0,0 +1,38 @@
+{
+    "input/multiple_declarations/no_arch": {
+        "test_name": "input/multiple_declarations/no_arch",
+        "blif": "multiple_declarations.blif",
+        "exit": 134,
+        "errors": [
+            "OUTPUT_BLIF More lines (8) than values (7)."
+        ]
+    },
+    "DEFAULT": {
+        "test_name": "n/a",
+        "architecture": "n/a",
+        "blif": "n/a",
+        "exit": 0,
+        "leaks": 0,
+        "errors": [],
+        "warnings": [],
+        "expectation": [],
+        "max_rss(MiB)": -1,
+        "exec_time(ms)": -1,
+        "simulation_time(ms)": -1,
+        "test_coverage(%)": -1,
+        "Latch Drivers": 0,
+        "Pi": 0,
+        "Po": 0,
+        "logic element": 0,
+        "latch": 0,
+        "Adder": -1,
+        "Multiplier": -1,
+        "Memory": -1,
+        "Hard Ip": -1,
+        "generic logic size": -1,
+        "Longest Path": 0,
+        "Average Path": 0,
+        "Estimated LUTs": 0,
+        "Total Node": 0
+    }
+}
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/input/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/keywords/input/synthesis_result.json
index fbdc7a3397d..dbc0ffa0e1d 100644
--- a/ODIN_II/regression_test/benchmark/task/keywords/input/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/keywords/input/synthesis_result.json
@@ -10,10 +10,18 @@
     "input/multiple_declarations/no_arch": {
         "test_name": "input/multiple_declarations/no_arch",
         "verilog": "multiple_declarations.v",
-        "exit": 134,
-        "errors": [
-            "AST multiple_declarations.v:3 Odin does not handle signed nets (a)"
-        ]
+        "warnings": [
+            "AST multiple_declarations.v:3 Odin does not handle signed WIRE (a)",
+            "AST multiple_declarations.v:3 Odin does not handle signed WIRE (b)",
+            "AST multiple_declarations.v:3 Odin does not handle signed WIRE (c)",
+            "AST multiple_declarations.v:7 Odin does not handle signed WIRE (h)",
+            "AST multiple_declarations.v:7 Odin does not handle signed WIRE (i)",
+            "AST multiple_declarations.v:7 Odin does not handle signed WIRE (j)"
+        ],
+        "Pi": 11,
+        "Po": 11,
+        "Longest Path": 2,
+        "Average Path": 2
     },
     "DEFAULT": {
         "test_name": "n/a",
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/integer/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/integer/simulation_result.json
new file mode 100644
index 00000000000..7fae40dde85
--- /dev/null
+++ b/ODIN_II/regression_test/benchmark/task/keywords/integer/simulation_result.json
@@ -0,0 +1,61 @@
+{
+    "integer/integer_outside/no_arch": {
+        "test_name": "integer/integer_outside/no_arch",
+        "blif": "integer_outside.blif",
+        "exit": 134,
+        "errors": [
+            "OUTPUT_BLIF Vector files differ."
+        ],
+        "warnings": [
+            "OUTPUT_BLIF Vector 0 mismatch:",
+            "OUTPUT_BLIF Vector 1 mismatch:",
+            "OUTPUT_BLIF Vector 2 mismatch:",
+            "OUTPUT_BLIF Vector 3 mismatch:",
+            "OUTPUT_BLIF Vector 4 mismatch:",
+            "OUTPUT_BLIF Vector 5 mismatch:"
+        ]
+    },
+    "integer/integer_port/no_arch": {
+        "test_name": "integer/integer_port/no_arch",
+        "blif": "integer_port.blif",
+        "exit": 134,
+        "errors": [
+            "OUTPUT_BLIF Vector files differ."
+        ],
+        "warnings": [
+            "OUTPUT_BLIF Vector 0 mismatch:",
+            "OUTPUT_BLIF Vector 1 mismatch:",
+            "OUTPUT_BLIF Vector 3 mismatch:",
+            "OUTPUT_BLIF Vector 4 mismatch:",
+            "OUTPUT_BLIF Vector 5 mismatch:"
+        ]
+    },
+    "DEFAULT": {
+        "test_name": "n/a",
+        "architecture": "n/a",
+        "blif": "n/a",
+        "exit": 0,
+        "leaks": 0,
+        "errors": [],
+        "warnings": [],
+        "expectation": [],
+        "max_rss(MiB)": -1,
+        "exec_time(ms)": -1,
+        "simulation_time(ms)": -1,
+        "test_coverage(%)": -1,
+        "Latch Drivers": 0,
+        "Pi": 0,
+        "Po": 0,
+        "logic element": 0,
+        "latch": 0,
+        "Adder": -1,
+        "Multiplier": -1,
+        "Memory": -1,
+        "Hard Ip": -1,
+        "generic logic size": -1,
+        "Longest Path": 0,
+        "Average Path": 0,
+        "Estimated LUTs": 0,
+        "Total Node": 0
+    }
+}
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/integer/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/keywords/integer/synthesis_result.json
index 21fccd0dfdc..171fc89e427 100644
--- a/ODIN_II/regression_test/benchmark/task/keywords/integer/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/keywords/integer/synthesis_result.json
@@ -4,24 +4,57 @@
         "verilog": "integer_failure.v",
         "exit": 134,
         "errors": [
-            "AST integer_failure.v:3 Odin does not handle signed ports (a)"
+            "NETLIST integer_failure.v:3 Input cannot be defined as a reg"
+        ],
+        "warnings": [
+            "AST integer_failure.v:3 Odin does not handle signed REG (a)",
+            "AST integer_failure.v:3 Odin does not handle signed INPUT (a)",
+            "AST integer_failure.v:3 Odin does not handle signed ports (a)",
+            "AST integer_failure.v:4 Odin does not handle signed REG (b)",
+            "AST integer_failure.v:4 Odin does not handle signed INPUT (b)",
+            "AST integer_failure.v:4 Odin does not handle signed ports (b)",
+            "AST integer_failure.v:6 Odin does not handle signed REG (c)",
+            "AST integer_failure.v:6 Odin does not handle signed OUTPUT (c)",
+            "AST integer_failure.v:6 Odin does not handle signed ports (c)"
         ]
     },
     "integer/integer_outside/no_arch": {
         "test_name": "integer/integer_outside/no_arch",
         "verilog": "integer_outside.v",
-        "exit": 134,
-        "errors": [
-            "AST integer_outside.v:3 Odin does not handle signed ports (a)"
-        ]
+        "warnings": [
+            "AST integer_outside.v:3 Odin does not handle signed INPUT (a)",
+            "AST integer_outside.v:3 Odin does not handle signed ports (a)",
+            "AST integer_outside.v:4 Odin does not handle signed INPUT (b)",
+            "AST integer_outside.v:4 Odin does not handle signed ports (b)",
+            "AST integer_outside.v:8 Odin does not handle signed REG (c)"
+        ],
+        "Pi": 2,
+        "Po": 1,
+        "logic element": 1,
+        "Longest Path": 3,
+        "Average Path": 3,
+        "Estimated LUTs": 1,
+        "Total Node": 1
     },
     "integer/integer_port/no_arch": {
         "test_name": "integer/integer_port/no_arch",
         "verilog": "integer_port.v",
-        "exit": 134,
-        "errors": [
-            "AST integer_port.v:3 Odin does not handle signed ports (a)"
-        ]
+        "warnings": [
+            "AST integer_port.v:3 Odin does not handle signed INPUT (a)",
+            "AST integer_port.v:3 Odin does not handle signed ports (a)",
+            "AST integer_port.v:4 Odin does not handle signed INPUT (b)",
+            "AST integer_port.v:4 Odin does not handle signed ports (b)",
+            "AST integer_port.v:6 Odin does not handle signed REG (c)",
+            "AST integer_port.v:6 Odin does not handle signed OUTPUT (c)",
+            "AST integer_port.v:6 Odin does not handle signed ports (c)"
+        ],
+        "Pi": 32,
+        "Po": 32,
+        "logic element": 33,
+        "Longest Path": 19,
+        "Average Path": 3,
+        "Estimated LUTs": 33,
+        "Total Node": 33
     },
     "DEFAULT": {
         "test_name": "n/a",
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/output/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/output/simulation_result.json
new file mode 100644
index 00000000000..8ed500b79b1
--- /dev/null
+++ b/ODIN_II/regression_test/benchmark/task/keywords/output/simulation_result.json
@@ -0,0 +1,38 @@
+{
+    "output/multiple_declarations/no_arch": {
+        "test_name": "output/multiple_declarations/no_arch",
+        "blif": "multiple_declarations.blif",
+        "exit": 134,
+        "errors": [
+            "OUTPUT_BLIF More lines (8) than values (7)."
+        ]
+    },
+    "DEFAULT": {
+        "test_name": "n/a",
+        "architecture": "n/a",
+        "blif": "n/a",
+        "exit": 0,
+        "leaks": 0,
+        "errors": [],
+        "warnings": [],
+        "expectation": [],
+        "max_rss(MiB)": -1,
+        "exec_time(ms)": -1,
+        "simulation_time(ms)": -1,
+        "test_coverage(%)": -1,
+        "Latch Drivers": 0,
+        "Pi": 0,
+        "Po": 0,
+        "logic element": 0,
+        "latch": 0,
+        "Adder": -1,
+        "Multiplier": -1,
+        "Memory": -1,
+        "Hard Ip": -1,
+        "generic logic size": -1,
+        "Longest Path": 0,
+        "Average Path": 0,
+        "Estimated LUTs": 0,
+        "Total Node": 0
+    }
+}
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/output/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/keywords/output/synthesis_result.json
index fd71a8d1e68..838f3658b70 100644
--- a/ODIN_II/regression_test/benchmark/task/keywords/output/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/keywords/output/synthesis_result.json
@@ -2,10 +2,18 @@
     "output/multiple_declarations/no_arch": {
         "test_name": "output/multiple_declarations/no_arch",
         "verilog": "multiple_declarations.v",
-        "exit": 134,
-        "errors": [
-            "AST multiple_declarations.v:3 Odin does not handle signed nets (a)"
-        ]
+        "warnings": [
+            "AST multiple_declarations.v:3 Odin does not handle signed WIRE (a)",
+            "AST multiple_declarations.v:3 Odin does not handle signed WIRE (b)",
+            "AST multiple_declarations.v:3 Odin does not handle signed WIRE (c)",
+            "AST multiple_declarations.v:7 Odin does not handle signed WIRE (h)",
+            "AST multiple_declarations.v:7 Odin does not handle signed WIRE (i)",
+            "AST multiple_declarations.v:7 Odin does not handle signed WIRE (j)"
+        ],
+        "Pi": 11,
+        "Po": 11,
+        "Longest Path": 2,
+        "Average Path": 2
     },
     "output/output_port_failure/no_arch": {
         "test_name": "output/output_port_failure/no_arch",
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/parameter/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/keywords/parameter/synthesis_result.json
index e9e89876deb..28567e7ad81 100644
--- a/ODIN_II/regression_test/benchmark/task/keywords/parameter/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/keywords/parameter/synthesis_result.json
@@ -14,6 +14,7 @@
         "test_name": "parameter/parameter_define/no_arch",
         "verilog": "parameter_define.v",
         "warnings": [
+            "AST parameter_define.v:7 Odin does not handle signed REG (i)",
             "NETLIST parameter_define.v:6 This output is undriven (simple_op^out~4) and will be removed",
             "NETLIST parameter_define.v:6 Net simple_op^out~4 driving node simple_op^out~4 is itself undriven."
         ],
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/simulation_result.json
new file mode 100644
index 00000000000..051cd23626a
--- /dev/null
+++ b/ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/simulation_result.json
@@ -0,0 +1,88 @@
+{
+    "signed_unsigned/signed_to_signed/no_arch": {
+        "test_name": "signed_unsigned/signed_to_signed/no_arch",
+        "blif": "signed_to_signed.blif",
+        "exit": 134,
+        "errors": [
+            "OUTPUT_BLIF Vector files differ."
+        ],
+        "warnings": [
+            "OUTPUT_BLIF Vector 0 mismatch:",
+            "OUTPUT_BLIF Vector 1 mismatch:",
+            "OUTPUT_BLIF Vector 4 mismatch:",
+            "OUTPUT_BLIF Vector 5 mismatch:"
+        ]
+    },
+    "signed_unsigned/signed_to_unsigned/no_arch": {
+        "test_name": "signed_unsigned/signed_to_unsigned/no_arch",
+        "blif": "signed_to_unsigned.blif",
+        "exit": 134,
+        "errors": [
+            "OUTPUT_BLIF Vector files differ."
+        ],
+        "warnings": [
+            "OUTPUT_BLIF Vector 0 mismatch:",
+            "OUTPUT_BLIF Vector 1 mismatch:",
+            "OUTPUT_BLIF Vector 4 mismatch:",
+            "OUTPUT_BLIF Vector 5 mismatch:"
+        ]
+    },
+    "signed_unsigned/unsigned_to_signed/no_arch": {
+        "test_name": "signed_unsigned/unsigned_to_signed/no_arch",
+        "blif": "unsigned_to_signed.blif",
+        "max_rss(MiB)": 29.8,
+        "exec_time(ms)": 3.9,
+        "simulation_time(ms)": 0.7,
+        "test_coverage(%)": 100,
+        "Pi": 4,
+        "Po": 6,
+        "logic element": 6,
+        "Longest Path": 3,
+        "Average Path": 3,
+        "Estimated LUTs": 6,
+        "Total Node": 6
+    },
+    "signed_unsigned/unsigned_to_unsigned/no_arch": {
+        "test_name": "signed_unsigned/unsigned_to_unsigned/no_arch",
+        "blif": "unsigned_to_unsigned.blif",
+        "max_rss(MiB)": 30.2,
+        "exec_time(ms)": 3.3,
+        "simulation_time(ms)": 0.5,
+        "test_coverage(%)": 100,
+        "Pi": 4,
+        "Po": 6,
+        "logic element": 6,
+        "Longest Path": 3,
+        "Average Path": 3,
+        "Estimated LUTs": 6,
+        "Total Node": 6
+    },
+    "DEFAULT": {
+        "test_name": "n/a",
+        "architecture": "n/a",
+        "blif": "n/a",
+        "exit": 0,
+        "leaks": 0,
+        "errors": [],
+        "warnings": [],
+        "expectation": [],
+        "max_rss(MiB)": -1,
+        "exec_time(ms)": -1,
+        "simulation_time(ms)": -1,
+        "test_coverage(%)": -1,
+        "Latch Drivers": 0,
+        "Pi": 0,
+        "Po": 0,
+        "logic element": 0,
+        "latch": 0,
+        "Adder": -1,
+        "Multiplier": -1,
+        "Memory": -1,
+        "Hard Ip": -1,
+        "generic logic size": -1,
+        "Longest Path": 0,
+        "Average Path": 0,
+        "Estimated LUTs": 0,
+        "Total Node": 0
+    }
+}
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/synthesis_result.json
index 58e720c1894..a7e6b7ec4a7 100644
--- a/ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/synthesis_result.json
@@ -2,41 +2,48 @@
     "signed_unsigned/signed_to_signed/no_arch": {
         "test_name": "signed_unsigned/signed_to_signed/no_arch",
         "verilog": "signed_to_signed.v",
-        "exit": 134,
-        "errors": [
-            "AST signed_to_signed.v:2 Odin does not handle signed ports (a)"
-        ]
+        "warnings": [
+            "AST signed_to_signed.v:2 Odin does not handle signed INPUT (a)",
+            "AST signed_to_signed.v:2 Odin does not handle signed ports (a)",
+            "AST signed_to_signed.v:3 Odin does not handle signed OUTPUT (b)",
+            "AST signed_to_signed.v:3 Odin does not handle signed ports (b)"
+        ],
+        "Pi": 4,
+        "Po": 6,
+        "Longest Path": 2,
+        "Average Path": 2
     },
     "signed_unsigned/signed_to_unsigned/no_arch": {
         "test_name": "signed_unsigned/signed_to_unsigned/no_arch",
         "verilog": "signed_to_unsigned.v",
-        "exit": 134,
-        "errors": [
+        "warnings": [
+            "AST signed_to_unsigned.v:2 Odin does not handle signed INPUT (a)",
             "AST signed_to_unsigned.v:2 Odin does not handle signed ports (a)"
-        ]
+        ],
+        "Pi": 4,
+        "Po": 6,
+        "Longest Path": 2,
+        "Average Path": 2
     },
     "signed_unsigned/unsigned_to_signed/no_arch": {
         "test_name": "signed_unsigned/unsigned_to_signed/no_arch",
         "verilog": "unsigned_to_signed.v",
-        "exit": 134,
-        "errors": [
+        "warnings": [
+            "AST unsigned_to_signed.v:3 Odin does not handle signed OUTPUT (b)",
             "AST unsigned_to_signed.v:3 Odin does not handle signed ports (b)"
         ],
-        "warnings": [
-            "PARSE_TO_AST unsigned_to_signed.v:2 error in parsing: (syntax error, unexpected '[', expecting ';' or ',')"
-        ]
+        "Pi": 4,
+        "Po": 6,
+        "Longest Path": 2,
+        "Average Path": 2
     },
     "signed_unsigned/unsigned_to_unsigned/no_arch": {
         "test_name": "signed_unsigned/unsigned_to_unsigned/no_arch",
         "verilog": "unsigned_to_unsigned.v",
-        "exit": 134,
-        "errors": [
-            "AST unsigned_to_unsigned.v:1 No matching declaration for port a"
-        ],
-        "warnings": [
-            "PARSE_TO_AST unsigned_to_unsigned.v:2 error in parsing: (syntax error, unexpected '[', expecting ';' or ',')",
-            "PARSE_TO_AST unsigned_to_unsigned.v:3 error in parsing: (syntax error, unexpected '[', expecting ';' or ',')"
-        ]
+        "Pi": 4,
+        "Po": 6,
+        "Longest Path": 2,
+        "Average Path": 2
     },
     "DEFAULT": {
         "test_name": "n/a",
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/specify_endspecify/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/keywords/specify_endspecify/synthesis_result.json
index df22bef95fc..2c6bd1985be 100644
--- a/ODIN_II/regression_test/benchmark/task/keywords/specify_endspecify/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/keywords/specify_endspecify/synthesis_result.json
@@ -7,7 +7,7 @@
             "PARSE_TO_AST Parser found (4) errors in your syntax, exiting"
         ],
         "warnings": [
-            "PARSE_TO_AST specify_conditional.v:15 error in parsing: (syntax error, unexpected vIF, expecting vENDSPECIFY or vSPECPARAM or '(')",
+            "PARSE_TO_AST specify_conditional.v:15 error in parsing: (syntax error, unexpected vIF, expecting vSPECPARAM or vENDSPECIFY or '(')",
             "PARSE_TO_AST specify_conditional.v:16 error in parsing: (syntax error, unexpected '(')",
             "PARSE_TO_AST specify_conditional.v:17 error in parsing: (syntax error, unexpected '(')",
             "PARSE_TO_AST specify_conditional.v:18 error in parsing: (syntax error, unexpected '(')"
diff --git a/ODIN_II/regression_test/benchmark/task/keywords/while/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/keywords/while/synthesis_result.json
index a7dac114a6f..3eae9e3056f 100644
--- a/ODIN_II/regression_test/benchmark/task/keywords/while/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/keywords/while/synthesis_result.json
@@ -5,6 +5,9 @@
         "exit": 134,
         "errors": [
             "AST while_loop.v:13 While statements are NOT supported"
+        ],
+        "warnings": [
+            "AST while_loop.v:6 Odin does not handle signed REG (i)"
         ]
     },
     "DEFAULT": {
diff --git a/ODIN_II/regression_test/benchmark/task/micro/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/micro/synthesis_result.json
index 8202da6650f..308b0defe7b 100644
--- a/ODIN_II/regression_test/benchmark/task/micro/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/micro/synthesis_result.json
@@ -4130,6 +4130,10 @@
         "test_name": "micro/case_generate/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "case_generate.v",
+        "warnings": [
+            "AST case_generate.v:8 Odin does not handle signed GENVAR (i)",
+            "AST case_generate.v:9 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 29.4,
         "exec_time(ms)": 56.8,
         "synthesis_time(ms)": 11.4,
@@ -4145,6 +4149,10 @@
         "test_name": "micro/case_generate/k6_N10_40nm",
         "architecture": "k6_N10_40nm.xml",
         "verilog": "case_generate.v",
+        "warnings": [
+            "AST case_generate.v:8 Odin does not handle signed GENVAR (i)",
+            "AST case_generate.v:9 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 20.1,
         "exec_time(ms)": 18,
         "synthesis_time(ms)": 12.3,
@@ -4157,6 +4165,10 @@
         "test_name": "micro/case_generate/k6_N10_mem32K_40nm",
         "architecture": "k6_N10_mem32K_40nm.xml",
         "verilog": "case_generate.v",
+        "warnings": [
+            "AST case_generate.v:8 Odin does not handle signed GENVAR (i)",
+            "AST case_generate.v:9 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 28.9,
         "exec_time(ms)": 52.3,
         "synthesis_time(ms)": 11.6,
@@ -4170,6 +4182,10 @@
     "micro/case_generate/no_arch": {
         "test_name": "micro/case_generate/no_arch",
         "verilog": "case_generate.v",
+        "warnings": [
+            "AST case_generate.v:8 Odin does not handle signed GENVAR (i)",
+            "AST case_generate.v:9 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 17.7,
         "exec_time(ms)": 14.1,
         "synthesis_time(ms)": 12.7,
@@ -4256,6 +4272,10 @@
         "test_name": "micro/generate/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "generate.v",
+        "warnings": [
+            "AST generate.v:10 Odin does not handle signed GENVAR (i)",
+            "AST generate.v:11 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 29.5,
         "exec_time(ms)": 43.2,
         "synthesis_time(ms)": 8.1,
@@ -4277,6 +4297,10 @@
         "test_name": "micro/generate/k6_N10_40nm",
         "architecture": "k6_N10_40nm.xml",
         "verilog": "generate.v",
+        "warnings": [
+            "AST generate.v:10 Odin does not handle signed GENVAR (i)",
+            "AST generate.v:11 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 20,
         "exec_time(ms)": 15.8,
         "synthesis_time(ms)": 10.2,
@@ -4295,6 +4319,10 @@
         "test_name": "micro/generate/k6_N10_mem32K_40nm",
         "architecture": "k6_N10_mem32K_40nm.xml",
         "verilog": "generate.v",
+        "warnings": [
+            "AST generate.v:10 Odin does not handle signed GENVAR (i)",
+            "AST generate.v:11 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 29.2,
         "exec_time(ms)": 52,
         "synthesis_time(ms)": 11.2,
@@ -4314,6 +4342,10 @@
     "micro/generate/no_arch": {
         "test_name": "micro/generate/no_arch",
         "verilog": "generate.v",
+        "warnings": [
+            "AST generate.v:10 Odin does not handle signed GENVAR (i)",
+            "AST generate.v:11 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 17.7,
         "exec_time(ms)": 13.6,
         "synthesis_time(ms)": 12.2,
@@ -4331,6 +4363,10 @@
         "test_name": "micro/if_generate/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "if_generate.v",
+        "warnings": [
+            "AST if_generate.v:8 Odin does not handle signed GENVAR (i)",
+            "AST if_generate.v:9 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 30,
         "exec_time(ms)": 57.4,
         "synthesis_time(ms)": 12.4,
@@ -4346,6 +4382,10 @@
         "test_name": "micro/if_generate/k6_N10_40nm",
         "architecture": "k6_N10_40nm.xml",
         "verilog": "if_generate.v",
+        "warnings": [
+            "AST if_generate.v:8 Odin does not handle signed GENVAR (i)",
+            "AST if_generate.v:9 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 20.1,
         "exec_time(ms)": 18.5,
         "synthesis_time(ms)": 12.8,
@@ -4358,6 +4398,10 @@
         "test_name": "micro/if_generate/k6_N10_mem32K_40nm",
         "architecture": "k6_N10_mem32K_40nm.xml",
         "verilog": "if_generate.v",
+        "warnings": [
+            "AST if_generate.v:8 Odin does not handle signed GENVAR (i)",
+            "AST if_generate.v:9 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 29.4,
         "exec_time(ms)": 53.8,
         "synthesis_time(ms)": 12.4,
@@ -4371,6 +4415,10 @@
     "micro/if_generate/no_arch": {
         "test_name": "micro/if_generate/no_arch",
         "verilog": "if_generate.v",
+        "warnings": [
+            "AST if_generate.v:8 Odin does not handle signed GENVAR (i)",
+            "AST if_generate.v:9 Odin does not handle signed GENVAR (j)"
+        ],
         "max_rss(MiB)": 18.5,
         "exec_time(ms)": 12.7,
         "synthesis_time(ms)": 11.6,
diff --git a/ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json
index 44cb4a7682a..356d07574f3 100644
--- a/ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json
+++ b/ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json
@@ -3,6 +3,9 @@
         "test_name": "syntax/8_bit_for_pass_through/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "8_bit_for_pass_through.v",
+        "warnings": [
+            "AST 8_bit_for_pass_through.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 26.8,
         "exec_time(ms)": 51.8,
         "synthesis_time(ms)": 5.3,
@@ -24,6 +27,9 @@
         "test_name": "syntax/8_bit_for_pass_through_module/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "8_bit_for_pass_through_module.v",
+        "warnings": [
+            "AST 8_bit_for_pass_through_module.v:5 Odin does not handle signed GENVAR (i)"
+        ],
         "max_rss(MiB)": 28.8,
         "exec_time(ms)": 44.5,
         "synthesis_time(ms)": 7.2,
@@ -44,6 +50,9 @@
     "syntax/8_bit_for_pass_through_module/no_arch": {
         "test_name": "syntax/8_bit_for_pass_through_module/no_arch",
         "verilog": "8_bit_for_pass_through_module.v",
+        "warnings": [
+            "AST 8_bit_for_pass_through_module.v:5 Odin does not handle signed GENVAR (i)"
+        ],
         "max_rss(MiB)": 16,
         "exec_time(ms)": 9.8,
         "synthesis_time(ms)": 8.4,
@@ -60,6 +69,9 @@
     "syntax/8_bit_for_pass_through/no_arch": {
         "test_name": "syntax/8_bit_for_pass_through/no_arch",
         "verilog": "8_bit_for_pass_through.v",
+        "warnings": [
+            "AST 8_bit_for_pass_through.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 13.6,
         "exec_time(ms)": 10.4,
         "synthesis_time(ms)": 8.4,
@@ -77,6 +89,9 @@
         "test_name": "syntax/8_bit_for_pass_through_off_by_1/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "8_bit_for_pass_through_off_by_1.v",
+        "warnings": [
+            "AST 8_bit_for_pass_through_off_by_1.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 27.8,
         "exec_time(ms)": 54.8,
         "synthesis_time(ms)": 6.5,
@@ -97,6 +112,9 @@
     "syntax/8_bit_for_pass_through_off_by_1/no_arch": {
         "test_name": "syntax/8_bit_for_pass_through_off_by_1/no_arch",
         "verilog": "8_bit_for_pass_through_off_by_1.v",
+        "warnings": [
+            "AST 8_bit_for_pass_through_off_by_1.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 15.2,
         "exec_time(ms)": 8.9,
         "synthesis_time(ms)": 7.5,
@@ -599,6 +617,9 @@
         "test_name": "syntax/complex_post_for_loop/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "complex_post_for_loop.v",
+        "warnings": [
+            "AST complex_post_for_loop.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 26.9,
         "exec_time(ms)": 49.6,
         "synthesis_time(ms)": 5.5,
@@ -619,6 +640,9 @@
     "syntax/complex_post_for_loop/no_arch": {
         "test_name": "syntax/complex_post_for_loop/no_arch",
         "verilog": "complex_post_for_loop.v",
+        "warnings": [
+            "AST complex_post_for_loop.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 13.8,
         "exec_time(ms)": 7.3,
         "synthesis_time(ms)": 5.9,
@@ -672,11 +696,10 @@
         "verilog": "deassign.v",
         "exit": 134,
         "errors": [
-            "PARSE_TO_AST Parser found (2) errors in your syntax, exiting"
+            "PARSE_TO_AST Parser found (1) errors in your syntax, exiting"
         ],
         "warnings": [
-            "PARSE_TO_AST deassign.v:21 Unsuported token",
-            "PARSE_TO_AST deassign.v:21 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=')"
+            "PARSE_TO_AST deassign.v:21 error in parsing: (syntax error, unexpected vDEASSIGN)"
         ]
     },
     "syntax/deassign/no_arch": {
@@ -684,11 +707,10 @@
         "verilog": "deassign.v",
         "exit": 134,
         "errors": [
-            "PARSE_TO_AST Parser found (2) errors in your syntax, exiting"
+            "PARSE_TO_AST Parser found (1) errors in your syntax, exiting"
         ],
         "warnings": [
-            "PARSE_TO_AST deassign.v:21 Unsuported token",
-            "PARSE_TO_AST deassign.v:21 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=')"
+            "PARSE_TO_AST deassign.v:21 error in parsing: (syntax error, unexpected vDEASSIGN)"
         ]
     },
     "syntax/delay_syntax/k6_frac_N10_frac_chain_mem32K_40nm": {
@@ -893,6 +915,9 @@
         "test_name": "syntax/for_loop_adv_post/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "for_loop_adv_post.v",
+        "warnings": [
+            "AST for_loop_adv_post.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 26.2,
         "exec_time(ms)": 48.7,
         "synthesis_time(ms)": 3.8,
@@ -913,6 +938,9 @@
     "syntax/for_loop_adv_post/no_arch": {
         "test_name": "syntax/for_loop_adv_post/no_arch",
         "verilog": "for_loop_adv_post.v",
+        "warnings": [
+            "AST for_loop_adv_post.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 13,
         "exec_time(ms)": 5.8,
         "synthesis_time(ms)": 4.4,
@@ -930,6 +958,9 @@
         "test_name": "syntax/for_loop_adv_pre/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "for_loop_adv_pre.v",
+        "warnings": [
+            "AST for_loop_adv_pre.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 26.9,
         "exec_time(ms)": 49.5,
         "synthesis_time(ms)": 5.2,
@@ -950,6 +981,9 @@
     "syntax/for_loop_adv_pre/no_arch": {
         "test_name": "syntax/for_loop_adv_pre/no_arch",
         "verilog": "for_loop_adv_pre.v",
+        "warnings": [
+            "AST for_loop_adv_pre.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 13.7,
         "exec_time(ms)": 7.2,
         "synthesis_time(ms)": 5.9,
@@ -1053,7 +1087,9 @@
         ],
         "warnings": [
             "PARSE_TO_AST function_hdr.v:14 error in parsing: (syntax error, unexpected vINT_NUMBER, expecting vSYMBOL_ID or '{')",
-            "AST function_hdr.vh:13 ODIN_II does not fully support input/output integers in functions"
+            "AST function_hdr.v:15 Odin does not handle signed REG (output_int)",
+            "AST function_hdr.vh:2 Odin does not handle signed REG (func_out)",
+            "AST function_hdr.vh:5 Odin does not handle signed REG (test_int)"
         ]
     },
     "syntax/function_hdr/no_arch": {
@@ -1065,7 +1101,9 @@
         ],
         "warnings": [
             "PARSE_TO_AST function_hdr.v:14 error in parsing: (syntax error, unexpected vINT_NUMBER, expecting vSYMBOL_ID or '{')",
-            "AST function_hdr.vh:13 ODIN_II does not fully support input/output integers in functions"
+            "AST function_hdr.v:15 Odin does not handle signed REG (output_int)",
+            "AST function_hdr.vh:2 Odin does not handle signed REG (func_out)",
+            "AST function_hdr.vh:5 Odin does not handle signed REG (test_int)"
         ]
     },
     "syntax/function_syntax/k6_frac_N10_frac_chain_mem32K_40nm": {
@@ -1105,6 +1143,9 @@
         "test_name": "syntax/h7_of_8_bit_for_pass_through/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "h7_of_8_bit_for_pass_through.v",
+        "warnings": [
+            "AST h7_of_8_bit_for_pass_through.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 26.8,
         "exec_time(ms)": 45,
         "synthesis_time(ms)": 4.3,
@@ -1125,6 +1166,9 @@
     "syntax/h7_of_8_bit_for_pass_through/no_arch": {
         "test_name": "syntax/h7_of_8_bit_for_pass_through/no_arch",
         "verilog": "h7_of_8_bit_for_pass_through.v",
+        "warnings": [
+            "AST h7_of_8_bit_for_pass_through.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 13.4,
         "exec_time(ms)": 6.5,
         "synthesis_time(ms)": 5.2,
@@ -1582,6 +1626,9 @@
         "test_name": "syntax/l2_and_h2_of_8_bit_for_pass_through/k6_frac_N10_frac_chain_mem32K_40nm",
         "architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
         "verilog": "l2_and_h2_of_8_bit_for_pass_through.v",
+        "warnings": [
+            "AST l2_and_h2_of_8_bit_for_pass_through.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 26.4,
         "exec_time(ms)": 47.4,
         "synthesis_time(ms)": 4,
@@ -1602,6 +1649,9 @@
     "syntax/l2_and_h2_of_8_bit_for_pass_through/no_arch": {
         "test_name": "syntax/l2_and_h2_of_8_bit_for_pass_through/no_arch",
         "verilog": "l2_and_h2_of_8_bit_for_pass_through.v",
+        "warnings": [
+            "AST l2_and_h2_of_8_bit_for_pass_through.v:11 Odin does not handle signed REG (i)"
+        ],
         "max_rss(MiB)": 13,
         "exec_time(ms)": 5.8,
         "synthesis_time(ms)": 4.4,