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@hzeller hzeller commented Nov 3, 2022

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@github-actions github-actions bot added build Build system lang-make CMake/Make code labels Nov 3, 2022
@hzeller hzeller force-pushed the 20221103-update-to-c++-17 branch from 6aabf72 to ece8d27 Compare November 4, 2022 00:56
@github-actions github-actions bot added the VPR VPR FPGA Placement & Routing Tool label Nov 4, 2022
@heshpdx
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heshpdx commented Nov 15, 2022

This might help: #2203

@hzeller hzeller force-pushed the 20221103-update-to-c++-17 branch from ece8d27 to a2f26a4 Compare November 15, 2022 16:33
Plus small changes to make compiler happy.

Signed-off-by: Henner Zeller <hzeller@google.com>
@hzeller hzeller force-pushed the 20221103-update-to-c++-17 branch from a2f26a4 to c313635 Compare November 15, 2022 16:34
@tangxifan
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@hzeller Thanks for pioneering the effort.
As we discussed today, @Tulong4Dev and I will keep monitoring the status of CI and follow-up on any code changes required.

  • We will apply code changes on any build errors due to C++ syntax mismatches
  • We will report any compile out-of-date errors due to C++17 requirements. We will discuss in next weekly meeting.

Currently, it is running well.

@tangxifan
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@vaughnbetz CI is green for this PR. It look like we have no problem when leveling up the C++ standard requirement to C++17. Can we merge this PR? Thanks

@vaughnbetz vaughnbetz merged commit 6826caf into verilog-to-routing:master Feb 24, 2023
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4 participants