From 95df088a9797d6373c11f7d848ecdd3eaa23ecdd Mon Sep 17 00:00:00 2001 From: Gonzalo Larumbe <51021955+gmlarumbe@users.noreply.github.com> Date: Thu, 12 May 2022 03:21:47 +0200 Subject: [PATCH] Fix indentation of coverpoints (#1321) (#1766). * verilog-mode.el (verilog-at-constraint-p): Fix indentation of coverpoints (#1321) (#1766). Signed-off-by: Gonzalo Larumbe --- tests_ok/indent_covergroup_swan.v | 78 +++++++++++++++---------------- verilog-mode.el | 2 +- 2 files changed, 40 insertions(+), 40 deletions(-) diff --git a/tests_ok/indent_covergroup_swan.v b/tests_ok/indent_covergroup_swan.v index e00f6ca7..22a8b018 100644 --- a/tests_ok/indent_covergroup_swan.v +++ b/tests_ok/indent_covergroup_swan.v @@ -2,43 +2,43 @@ module m; bit [0:0] a, b, c; covergroup g; cp_ab: coverpoint {a,b} { - bins one = {1}; - bins two = {2}; - } - - cp_ab_if_c: coverpoint {a,b} iff c { - bins one = {1}; - bins two = {2}; - } - - cp_ab_if_c_slice: coverpoint {a,b} iff c[0] { - bins one = {1}; - bins two = {2}; - } - - cp_a_if_bc: coverpoint {a,b} iff {b,c} { - bins one = {1}; - bins two = {2}; - } - - cp_a_slice : coverpoint a[0] { - bins one = {1}; - bins two = {2}; - } - - cp_a_slice_if_b : coverpoint a[0] iff b { - bins one = {1}; - bins two = {2}; - } - - cp_a_if_b_slice : coverpoint a iff b[0] { - bins one = {1}; - bins two = {2}; - } - - cp_a_slice_if_b_slice : coverpoint a[0] iff b[0] { - bins one = {1}; - bins two = {2}; - } - endgroup + bins one = {1}; + bins two = {2}; + } + + cp_ab_if_c: coverpoint {a,b} iff c { + bins one = {1}; + bins two = {2}; + } + + cp_ab_if_c_slice: coverpoint {a,b} iff c[0] { + bins one = {1}; + bins two = {2}; + } + + cp_a_if_bc: coverpoint {a,b} iff {b,c} { + bins one = {1}; + bins two = {2}; + } + + cp_a_slice : coverpoint a[0] { + bins one = {1}; + bins two = {2}; + } + + cp_a_slice_if_b : coverpoint a[0] iff b { + bins one = {1}; + bins two = {2}; + } + + cp_a_if_b_slice : coverpoint a iff b[0] { + bins one = {1}; + bins two = {2}; + } + + cp_a_slice_if_b_slice : coverpoint a[0] iff b[0] { + bins one = {1}; + bins two = {2}; + } + endgroup endmodule diff --git a/verilog-mode.el b/verilog-mode.el index 7f877261..2061a86f 100644 --- a/verilog-mode.el +++ b/verilog-mode.el @@ -6646,7 +6646,7 @@ Also move point to constraint." )) ;; if first word token not keyword, it maybe the instance name ;; check next word token - (if (looking-at "\\<\\w+\\>\\|\\s-*(\\s-*\\S-+") + (if (looking-at "\\<\\w+\\>\\|\\s-*[\[(}]\\s-*\\S-+") (progn (verilog-beg-of-statement) (if (and (not (string-match verilog-named-block-re (buffer-substring pt (point)))) ;; Abort if 'begin' keyword is found