module top (/*AUTOARG*/);


/*AUTO_LISP(defvar sig -1) */ // Init Start value for sig
/*AUTO_LISP(defvar sig2 -1)*/ // Init Start Value for sig2

// function for increment, which take name of signal to increment
/*AUTO_LISP(defun testfunc (sig_name)
    (setq sig_name (+ sig_name 1 ))
)
*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [0:0]              sig;                    // From u_x of design1.v, ...
wire [0:0]              sig2;                   // From u_x of design1.v, ...
// End of automatics

/*
design1 AUTO_TEMPLATE 
design2 AUTO_TEMPLATE 
design3 AUTO_TEMPLATE (
  //.\(.*\)   (\1[@"(testfunc sig)"]),
  .\(.*\) (\1[@"(testfunc \1)"]),
); 
*/
design1 u_x (/*AUTOINST*/
             // Outputs
             .sig                       (sig[0]),                // Templated
             .sig2                      (sig2[0]));              // Templated
design2 u_y (/*AUTOINST*/
             // Outputs
             .sig2                      (sig2[0]));              // Templated
design3 u_z (/*AUTOINST*/
             // Outputs
             .sig                       (sig[0]));               // Templated

design1 u_a (/*AUTOINST*/
             // Outputs
             .sig                       (sig[0]),                // Templated
             .sig2                      (sig2[0]));              // Templated
design2 u_b (/*AUTOINST*/
             // Outputs
             .sig2                      (sig2[0]));              // Templated
design1 u_c (/*AUTOINST*/
             // Outputs
             .sig                       (sig[0]),                // Templated
             .sig2                      (sig2[0]));              // Templated

             
/*
final_sig AUTO_TEMPLATE (
  .WIDTH_1    (@"(testfunc sig)"-1),
  .WIDTH_2    (@"(testfunc sig2)"-1),
  .in_1       (sig[]),
  .in_2       (sig2[]),
); 
*/
             
final_sig #(/*AUTOINSTPARAM*/
            // Parameters
            .WIDTH_1                    (0-1),                   // Templated
            .WIDTH_2                    (0-1))                   // Templated
   u_dd(/*AUTOINST*/
        // Inputs
        .in_1                           (sig[(-1)-1:0]),         // Templated
        .in_2                           (sig2[(-1)-1:0]));       // Templated
endmodule


module top_exp (/*AUTOARG*/);


wire [3:0]              sig;                    // From u_c of design1.v
wire [4:0]              sig2;                   // From u_c of design1.v

design1 u_x (
             // Outputs
             .sig                       (sig[0]),
             .sig2                      (sig2[0]));
design2 u_y (
             // Outputs
             .sig2                      (sig2[1]));
design3 u_z (
             // Outputs
             .sig                       (sig[1]));

design1 u_a (
             // Outputs
             .sig                       (sig[2]),
             .sig2                      (sig2[2]));
design2 u_b (
             // Outputs
             .sig2                      (sig2[3]));
design1 u_c (
             // Outputs
             .sig                       (sig[3]),   
             .sig2                      (sig2[4])); 

             
final_sig #(.WIDTH_1 (4),
            .WIDTH_2 (5)
)
u_dd (
.in_1 (sig  [3:0]),
.in_2 (sig2 [4:0])
);
endmodule


module design1 (/*AUTOARG*/
   // Outputs
   sig, sig2
   );
output sig;
output sig2;

endmodule


module design2 (/*AUTOARG*/
   // Outputs
   sig2
   );
output sig2;

endmodule

module design3 (/*AUTOARG*/
   // Outputs
   sig
   );
output sig;

endmodule

module final_sig (/*AUTOARG*/
   // Inputs
   in_1, in_2
   )
parameter WIDTH_1 = 0;
parameter WIDTH_2 = 0;
input [WIDTH_1 -1:0] in_1;
input [WIDTH_2 -1:0] in_2;
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// End: