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AUTOOUTPUTEVERY and AUTOWIRE: Signal declared multiple times #1019
Author Name: Hanan Moller
When a wire (bus) is created due to AUTOINST + templates and then referred to using AUTOOUTPUTEVERY, the object is defined twice - once in the port declaration and once as a wire.
Can anyone please suggest a fix/workaround?
PS: Here's an example - the offending signal is "stage_2".
Original Redmine Comment
This is related to the order of AUTOs being processed. Basically AUTOOUTPUTEVERY is pretty fragile and was intended only for a debug aid.
I tried a fix back near when you filed this, and an attempted fix broke other tests, so more work is needed. I haven't gotten back to figuring out a more complicated fix, so wanted to reply before more time passes.