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Question: AUTO_TEMPLATE - queries #1049

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veripoolbot opened this issue Mar 26, 2016 · 7 comments
Closed

Question: AUTO_TEMPLATE - queries #1049

veripoolbot opened this issue Mar 26, 2016 · 7 comments
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@veripoolbot veripoolbot commented Mar 26, 2016


Author Name: kishore babu nainappagari
Original Redmine Message: 1833 from https://www.veripool.org


Hi Wilson,

I am having trouble to expand the below , using AUTO_TEMPLATE , Pls provide your suggestions

The expanded dut signals instantiation were either following the signals declarations hierarchy in the input file or getting sorted out using verilog-auto-inst-sort.

the expanded signals info was seen like below

.clnt29_clk ( clk_inst[29].clk),
.clnt30_clk ( clk_inst[30].clk),

.clnt29_wdata ( clk_inst[29].wdata),
.clnt30_wdata ( clk_inst[30].wdata),
...

However if I wish to have the signals info in the below format, May I know how can I do that.
//expected signals info

  .clnt30_clk ( clk_inst[30].clk),
  .clnt30_rst_n ( clk_inst[30].rst_n),
  .clnt30_wdata ( clk_inst[30].wdata),
  .clnt30_rdata ( clk_inst[30].rdata),

...
.clnt29_clk ( clk_inst[29].clk),
.clnt29_rst_n ( clk_inst[29].rst_n),
.clnt29_wdata ( clk_inst[29].wdata),
.clnt29_rdata ( clk_inst[29].rdata),

The expanded signals were seen like with improper number of white spaces

.blk_clnt0_rctl(clnt_inst[0].rctl[1:0]), // Templated
.blk_clnt0_rdata(clnt_inst[0].rdata[63:0]), // Templated
.blk_clnt0_rderr(clnt_inst[0].rderr), // Templated
.blk_clnt10_wstat_vld(clnt_inst[10].wstat_vld), // Templated

May I pls know how can I get the info in the below format (neatly aligned)

.blk_clnt0_rctl (clnt_inst[0].rctl[1:0]), // Templated
.blk_clnt0_rdata (clnt_inst[0].rdata[63:0]), // Templated
.blk_clnt0_rderr (clnt_inst[0].rderr), // Templated
.blk_clnt10_wstat_vld (clnt_inst[10].wstat_vld), // Templated

or at least in the below manner.

.blk_clnt0_rctl(clnt_inst[0].rctl[1:0]), // Templated
.blk_clnt0_rdata(clnt_inst[0].rdata[63:0]), // Templated
.blk_clnt0_rderr(clnt_inst[0].rderr), // Templated
.blk_clnt10_wstat_vld(clnt_inst[10].wstat_vld), // Templated

I have few signals like

.apb_blk_paddr (blk_apb_if_h.PADDR)
.apb_blk_pslverr (blk_apb_if_h.PSLVERR)
.apb_blk_pwdata (blk_apb_if_h.PWDATA)

I tried using syntax in AUTO_TEMPLATE, but it flags error.

.blk_apb_(.*) (blk_apb_if_h.@"(upcase \1)"[]),

However when I tried below, I was successful. but pls let me know if there is a better way to deal with these.

.blk_apb_(.*) (blk_apb_if_h.@"(substring (upcase vl-name) 8)"[])

The block has few parameters which I was able to get them using AUTOINSTPARAM like below

blk blk_i #(/AUTOINSTPARAM/
// Parameters
.SUPPORT (SUPPORT))(
...

however if I wish to get it like below, may I pls know if there is a way

blk blk_i #(/AUTOINSTPARAM/
// Parameters
.SUPPORT (blk_pkg::SUPPORT))(
...

Pls suggest.

rgds
Kishore

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@veripoolbot veripoolbot commented Mar 30, 2016


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-03-30T18:48:59Z


  1. You need the lisp to be properly quoted

.blk_apb_(.*) (blk_apb_if_h.@"(upcase \"\1\")"[]),

  1. There is at present no way to alter the sort order this way.

3/4. The mode will use the indentation of the ( opening the signals. So do this


  cellname
     #(/*AUTOPARAM*/)
    instname
     (/*AUTOINST*/);


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@veripoolbot veripoolbot commented Mar 30, 2016


Original Redmine Comment
Author Name: kishore babu nainappagari
Original Date: 2016-03-30T21:19:57Z


Hi Wilson,

Thanks for your suggestions.

Am sorry, I didn't get your last suggestion. Did you mean to say, both my indentation problem as well as the picking parameters value from package will be resolved if I use below.

cellname
#(/AUTOPARAM/)
instname
(/AUTOINST/);

I tried using AUTOPARAM but that's doesn't help.

can you pls elaborate it.

Thank you

rgds
Kishore

@veripoolbot veripoolbot closed this Apr 1, 2016
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@veripoolbot veripoolbot commented Apr 1, 2016


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-04-01T10:52:36Z


There is no automatic way to get parameters from a package. You can use AUTO_TEMPLATE (which applies to both parameters and normal signals) to either explicitly list them, or use a wildcard template to add them.

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@veripoolbot veripoolbot commented Apr 5, 2016


Original Redmine Comment
Author Name: kishore babu nainappagari
Original Date: 2016-04-05T01:19:48Z


Thanks for the info Wilson.

I was trying to use the below to see if I can get the value of the parameters while I expand the auto's

// Local Variables:
// verilog-auto-inst-param-value:t

However I still see the parameter name used in the expanded code. May I pls know if you have any suggestions in this regard. The design file had the parameters info like below.

The design file has the parameters defined like below

module abc (signal_a, signal_b...
);
parameter p1 = 64;
parameter p2 = 0;
...

endmodule

rgds
Kishore

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@veripoolbot veripoolbot commented Apr 6, 2016


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-04-06T10:33:36Z


verilog-auto-inst-param-value only affects AUTOINSTPARAM which you didn't have in your example; there's an example under "M-x describe-variable auto-inst-param-value". If you still think it should work attach a complete example please.

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@veripoolbot veripoolbot commented Apr 26, 2016


Original Redmine Comment
Author Name: kishore babu nainappagari
Original Date: 2016-04-26T18:27:08Z


Hi Wilson,

Yeah, I used the AUTOINSTPARAM. Also I looked at the FAQ's and it looks I am following the steps suggested, but wondering why parameters value doesn't get the substituted during instantiation. Pls suggest me if I am missing anything here.

Pls find the info that I have used. AUTO_TEMPLATE had few more signals, I have trimmed them to avoid lengthy email

 /*AUTOWIRE*/

  /*
     mc_top AUTO_TEMPLATE (
       .mc_clk			     (clk),
       .mc_rstn		              (rst_n),
       .ahb_cfg_hclk                   (clk), 
       .ahb_cfg_\(.*\)_i               (ddr_ahb_master_if.@"(substring (upcase vl-name) 8 -2)"[]),
         .\(.*\)_scan_in               (),
       .axi0_\(.*\)AR\(.*\)PARIT\(.*\) (({@"vl-width"{1'b0}})),
       .axi0_\(.*\)W\(.*\)PARIT\(.*\)  (({@"vl-width"{1'b0}})),
       .axi0_\(.*\)\(.*\)PARIT\(.*\)   (),
       .axi0_\(.*\)_\(.*\)             (mctop_axi_master_if.@"(substring (upcase vl-name) 5 -2)"[]), 
       );
  */ 
    mc_top
          #(/*AUTOINSTPARAM*/)  
        mc_top_i 
	 ( /*AUTOINST*/);


at the end of the file, I had this info. 
    // Local Variables:
    // verilog-library-directories:("." 
    //     "../../rtl"
    // )
    // verilog-auto-inst-param-value: t
    // End:

And the rtl had parameters info in the below format:

module mc_top (mc_clk, mc_rstn, ...

);


parameter		P1 = 64;//  64
parameter		P1 = 0;

input mc_clk;
...
output  [P1:0]         axi0_data;
...

endmodule

rgds
Kishore

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@veripoolbot veripoolbot commented Apr 27, 2016


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-04-27T03:16:27Z


Sorry, I may have confused you. It reads the value of the parameter from a handcrafted value in the parameters in the instantiation. Like this - note the 15 in axi0_data. A case could be made to improve this.

module mc_top ();
    parameter        P1 = 64;
    output [P1:0] axi0_data;
endmodule

module x;
    mc_top
      #(.P1                              (15))
    mc_top_i
      ( /*AUTOINST*/
       // Outputs
       .axi0_data                        (axi0_data[15:0]));
endmodule;

// Local Variables:
// verilog-auto-inst-param-value:t
// End:

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