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Besides ignore regex, need force regex for auto-output #1085

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veripoolbot opened this issue Aug 27, 2016 · 4 comments
Open

Besides ignore regex, need force regex for auto-output #1085

veripoolbot opened this issue Aug 27, 2016 · 4 comments
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@veripoolbot veripoolbot commented Aug 27, 2016


Author Name: Terrence Sun
Original Redmine Issue: 1085 from https://www.veripool.org


If a signal is sub-module's input, then it is excluded from auto output.

I would like to add a verilog-auto-force-regex variable, and always output signal matches it.

For instance, do below changes to the sig-list generate:

-(verilog-subdecls-get-inputs modsubdecls)
+(verilog-signals-not-matching-regex (verilog-subdecls-get-inputs modsubdecls) verilog-auto-output-force-regexp)

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@veripoolbot veripoolbot commented Aug 30, 2016


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-08-30T01:02:56Z


Rather than a force, which is sort of a don't not include something, how about a verilog-auto-subdecl-regexp or something that defaults to .*, I.e. by default exclude all sub signals?

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@veripoolbot veripoolbot commented Aug 30, 2016


Original Redmine Comment
Author Name: Terrence Sun
Original Date: 2016-08-30T02:30:20Z


Wilson Snyder wrote:

Rather than a force, which is sort of a don't not include something, how about a verilog-auto-subdecl-regexp or something that defaults to ., I.e. by default exclude all sub signals?
By using '.
', the same as before.
By using '!(paddr|pwrite|pwdata)', we export paddr, pwrite and pwdata to the output.
This is workable, but the 'not' in regex make it less straightforward. Maybe we can pick another name for it.

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@veripoolbot veripoolbot commented Sep 10, 2016


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-09-10T23:53:45Z


I suspect an AUTOOUTPUT followed by AUTOOUTPUTEVERY("(paddr|pwrite|pwdata)") will do what you want. If not can you please attach a small verilog module showing a realistic case with what you want to do (I understand the solution you propose, just not the use case.)

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@veripoolbot veripoolbot commented Sep 11, 2016


Original Redmine Comment
Author Name: Terrence Sun
Original Date: 2016-09-11T02:57:04Z


Use-case:

  1. apb wrapper

We have two modules: ahb to apb mux (ahb2apb) and apb async bridge (apb_async).

ahb2apb can be connected to 32 apb slaves, and some of them are from different clock domain.

We make a wrapper (apb_wrapper) to instance one ahb2apb and multiple apb_async according to clock structure, so as to make chip top more clear.

We also make a apb_slave_map module to map ahb2apb.psel[31:0] to individual slave selector (for example, psel_gpio, psel_uart).

  • gpio has single clock, so a asyn bridge is needed.

  • uart has apb clock and uart clock, so direct connect it.

So, the topology of apb_wrapper is as below :

ahb2apb <-> apb_slave_map <-> apb_asyc_uart1 <->| connect to gpio of gpio clock (psel_gpio/paddr/pwrite/pwdata from apb_aysc_uart1)
                           <->                   | connect to uart of apb clock (psel_uart from apb_slave_map, paddr/pwrite/pwdate from ahb2apb)

ahb2apb.psel[31:0] is never needed to be exported as output, only paddr/pwrite/pwdata is needed.

So, OUTPUTEVERY is not suitable here.

  1. export busy flag for system control

Busy flag can be read back by CPU from apb bus, and also needed by clock control module for clock management.

So, for the top of a SOC component, engine_busy is connected to the apb slave sub-module as input, and also exported as output (for clock control).

For this case, only the engine_busy is need to exported.

These use-cases show that, only selected part of signals needed to export as output, and they are highly depending on the architecture of design.

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