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there are 2 spaces at the left side of "=" while : verilog-auto-lineup = all #1128

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veripoolbot opened this issue Feb 9, 2017 · 4 comments
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@veripoolbot veripoolbot commented Feb 9, 2017


Author Name: yun he
Original Redmine Issue: 1128 from https://www.veripool.org


type the code included below:

 module;

     abci = 1;
     ef = 2;

 endmodule

I expected:


     abci = 1;
     ef   = 2;

endmodule

but instead :


     abci  = 1;// there are at least 2 spaces at the left side of "="
     ef   = 2;

endmodule

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@veripoolbot veripoolbot commented May 8, 2017


Original Redmine Comment
Author Name: Kaushal Modi
Original Date: 2017-05-08T18:21:38Z


This is intentional from what I understand after studying the @verilog-pretty-expr@ function.

The extra space is put so that blocking and non-blocking assignments get lined up identically (though I don't know why one would have blocking and non-blocking assignments in the same block :P).

For instance, with point on "foo",

module;

    foo = 1;
    bar <= 1;
    
endmodule

running @verilog-pretty-expr@ (bound to @c-c =@), we get:

module;

    foo  = 1;
    bar <= 1;
    
endmodule

Here is the relevant code in @verilog-mode.el@:

(if (not (or (verilog-in-parenthesis-p)  ; leave attributes and comparisons alone
              (verilog-in-coverage-p)))
     (if (eq (char-after) ?=)
         (indent-to (1+ ind))	; line up the = of the <= with surrounding =
       (indent-to ind)
       ))

"Source":

verilog-mode/verilog-mode.el

Lines 7059 to 7064 in 685bba6

(if (not (or (verilog-in-parenthesis-p) ; leave attributes and comparisons alone
(verilog-in-coverage-p)))
(if (eq (char-after) ?=)
(indent-to (1+ ind)) ; line up the = of the <= with surrounding =
(indent-to ind)
))

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@veripoolbot veripoolbot commented May 8, 2017


Original Redmine Comment
Author Name: Kaushal Modi
Original Date: 2017-05-08T23:54:19Z


I have fixed this in "github/verilog-mode PR#15":#15

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@veripoolbot veripoolbot commented May 9, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-05-09T00:02:31Z


Looks good, thanks for digging into this.

Since you're patching, could you update it to add a proper docstring to verilog-get-lineup-indent-2 that mentions MYRE B and E (see M-x checkdoc report). Also please always have a space after ;, e.g. not ";Must" but "; Must". If you prefer I can clean these up before merging.

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@veripoolbot veripoolbot commented May 9, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-05-09T16:52:45Z


Thanks, pushed to git and 2017-05-09-eb40517-vpo.

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