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Author Name: Warren Ferguson
I entered the following file and allowed verilog mode (latest verilog-mode.el) to choose its own alignment. Why is the first generate-if using always_comb choosing the unusual alignment of the else block, whereas the generate-if using assigns has the expected alignment?
Original Redmine Comment
Verilog-mode seems to mis-assume always_comb is left-most inside a module.
There might be a wait, generally indentation fixes will need to wait for someone to provide a patch.