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SystemVerilog interface indentation in module declaration #1446

veripoolbot opened this issue May 23, 2019 · 2 comments

SystemVerilog interface indentation in module declaration #1446

veripoolbot opened this issue May 23, 2019 · 2 comments


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Author Name: Clarke Watson
Original Redmine Issue: 1446 from


Thanks for creating and maintaining verilog-mode. It is awesome!

I am having trouble getting SystemVerilog interfaces inside module declarations to indent properly when using verilog-batch-indent.

See attached sample code.

I would expect the din and dout interfaces to be aligned with the same column as the discrete logic signals after running verilog-batch-indent, but there always seems to be just a single space between the port type (SV interface) and the port name.

Let me know if I am missing a setting in the verilog-mode.el file.


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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-29T22:49:44Z

Agreed it should indent as you indicate, in general this looks to verilog-mode like a user-defined type, which is misindented due to #�.

Unfortunately unless you can contribute a patch, the indent part of verilog-mode is looking for a maintainer so it might be a long wait.

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I cannot see neither the code snippet nor the related issue. Is there a way to recover those to take a look at them?

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