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Expand AUTOINST default values for parameters #1447
Author Name: Mert Ustun
When I use verilog-auto-inst-param-value:t, it can successfully replace bus indexes with parameter values only if the parameter is explicitly assigned a value during the module instantiation. In many cases, parameter values could be left as default without any explicit setting, especially if the default value is inferred from another assigned parameter.
For instance, taking the example in Issue #522,
There is no need to set IDX_W parameter during instantiation since it's same as the default assigned value. However, verilog-auto-inst-param-value will not expand the param value if the parameter value is not explicitly set during instantiation.
I actually realized my request was already there in Issue #522, at the bottom:
_My next request would be to make it work:
These two conditions are very common and would be great if Verilog-mode could support parameter value expansion for these two cases.