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Describe how to find source file to debug autos #1471

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veripoolbot opened this issue Jun 21, 2019 · 3 comments
Closed

Describe how to find source file to debug autos #1471

veripoolbot opened this issue Jun 21, 2019 · 3 comments
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@veripoolbot veripoolbot commented Jun 21, 2019


Author Name: David Rogoff
Original Redmine Issue: 1471 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Hi.

Reading Issue #1464 reminded me of a debug feature that would be great. verilog-auto-inst-template-numbers is very helpful, but would would be really great would be for Verilog-auto to add a comment showing the filename/path where it got the instantiated file. I've been putting together some big, top-level wrapper modules and many sub-modules have versions in multiple directories. It was driving me nuts when ports weren't what I thought they should be until I realized what was going on and had to play with the order of Verilog-library-directories and make sure no other versions were open in emacs buffers.

Would this be easy to add?

Thanks,

David

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@veripoolbot veripoolbot commented Jun 21, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-21T21:39:11Z


This is doable, however I think an alternative that exists now may be as useful or more useful. Will shortly (unless you have rewordings) add this to the verilog-auto-inst docs:

"To debug what file a submodule comes from, in a buffer with AUTOINST use \[verilog-goto-defun] to switch buffers to the point containing the given symbol (i.e. a submodule name)'s module definition.

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@veripoolbot veripoolbot commented Jun 21, 2019


Original Redmine Comment
Author Name: David Rogoff
Original Date: 2019-06-21T21:43:02Z


Thanks - that should do the trick!

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@veripoolbot veripoolbot commented Jun 21, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-21T21:52:37Z


Great, docs pushed to git.

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