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Replacing instance port parameters with it's values in parent module ports - An issue with usage of verilog-auto-inst-param-value #1667

engrvns opened this issue Apr 21, 2020 · 1 comment


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engrvns commented Apr 21, 2020

Hi Wilson,
I am finding an issue with the verilog-mode where the parent module port definitions inherit the child parameter names.

This is inefficient and forces the user to -

  1. redefine the instance parameters at the instance level which is redundant
    2)Difficult to keep updating as ExampInst could be owned by another owner
    3)Difficult to maintain if there are lots of parameters and multiple instances...

In the example below, the ports of ExampInst are defined in terms of W.
Which would mean ExampInst wont's compile unless parameter W is re-defined.

This behavior happens due to requirements of verilog-auto-inst-param-value:t
How can we avoid this issue?

module InstModule
#(parameter W = 2)
input [W-1:0] i,
output[W-1:0] o

module ExampInst
// Beginning of automatic inputs (from unused autoinst inputs)
input [W-1:0] i, // To instName of InstModule.v
// End of automatics
// Beginning of automatic outputs (from unused autoinst outputs)
output [W-1:0] o // From instName of InstModule.v
// End of automatics
instName (/AUTOINST/
// Outputs
.o (o[W-1:0]),
// Inputs
.i (i[W-1:0]));
endmodule // ExampInst

// Local variables:
// verilog-auto-sense-defines-constant:t
// verilog-auto-inst-param-value:t
// End:

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wsnyder commented Apr 21, 2020

What behavior are you suggesting/recommending?

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