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Use of Ordered AUTO_TEMPLATEs to simplify code integration #1673

engrvns opened this issue Jun 6, 2020 · 3 comments

Use of Ordered AUTO_TEMPLATEs to simplify code integration #1673

engrvns opened this issue Jun 6, 2020 · 3 comments


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engrvns commented Jun 6, 2020

This is an enhancement proposal for existing verilog-mode which will be useful when code has Multiple instances of a Module(s) with large number of ports and deviations to a non-trivial subset of ports.

The current method(s) to handle this is -

Method 1: Define a common denominator AUTO_TEMPLATE for the module and define override custom connections at instantiation.
This definitely works. But custom connections would means the advantage of rule based connections are lost...

Method 2: Duplicate the entire AUTO_TEMPLATE and modify the rules for the subset,
This works as well. But code duplication, bloat and maintenance.

Am method would be to use ordered AUTO_TEMPLATE and have precedence rules define the final AUTO_TEMPLATE

  1. Define an common denominator AUTO_TEMPLATE
  2. Define an overlay AUTO_TEMPLATE for the "exception subset" and have precedence.

Refer attached example for a proposal ...


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wsnyder commented Jun 6, 2020

I can see how that's useful. I'd suggest instead that the "overlays" have some method to specify the "base". This is more flexible and easier to implement. The base is just then a normal AUTO_TEMPLATE. Probably want to use the word "extends" somehow as that's what SystemVerilog classes use.

/* base AUTO_TEMPLATE \(.*\) ( <- base auto_template
   .\(portA\) (\1_ruleA),
   .\(portB\) (\1_ruleB),
   .\(portC\) (\1_ruleC),
/* mod1 AUTO_TEMPLATE \(.*\) AUTO_EXTENDS(base) (
  .\(portB\) (\1_ruleB0), <- Rule based deviation for portB 

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engrvns commented Jun 6, 2020 via email

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engrvns commented Jun 29, 2020

Hi Wilson,

When do you think this feature will get into the release.
I can test it out if there is a beta version.

  • engrvns

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