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and the wrapping results from some code at the end of verilog-auto-inst (link).
If you use the default value for verilog-cexp-indent the alignment is consistent across both indent-region and verilog-auto-inst. If verilog-auto-inst could be coerced to reuse the logic of verilog-indent-line-relative that should resolve the first issue.
Is there a reason the code pulls the closing parenthesis and semicolon to the end of the final port?
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