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Indenting mismatch between verilog-auto and indent region with non-default verilog-cexp-indent #1697

abradd opened this issue Oct 3, 2020 · 0 comments


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abradd commented Oct 3, 2020

I'm running the latest commit (03ac87a).

If I set verilog-cexp-indent 2 and indent the code with indent-region (which uses verilog-indent-line-relative under the hood I believe), I get:

module to_inst(
  input clk,
  input rst_n,
  output logic out

endmodule // to_inst

module inst (/*AUTOARG*/);

  to_inst inst_example (

endmodule // inst

If I subsequently run verilog-auto the indentation on inst_example changes:

module inst (/*AUTOARG*/);

  to_inst inst_example (
                        // Outputs
                        .out            (out),
                        // Inputs
                        .clk            (clk),
                        .rst_n          (rst_n));

endmodule // inst

There are two issues as far as I can see:

  • the indentation is pushed to the opening paren of the port list (leaving the /*AUTOINST*/ behind)
  • the closing paren is wrapped to the right side of the last port

I took a look at the code and the first behavior is the result of this line in verilog-auto-inst (link):

 (indent-pt (save-excursion (verilog-backward-open-paren)
		      (1+ (current-column))))

and the wrapping results from some code at the end of verilog-auto-inst (link).

If you use the default value for verilog-cexp-indent the alignment is consistent across both indent-region and verilog-auto-inst. If verilog-auto-inst could be coerced to reuse the logic of verilog-indent-line-relative that should resolve the first issue.

Is there a reason the code pulls the closing parenthesis and semicolon to the end of the final port?


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