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What magic sauce is required to indent typedef's correctly? #1823

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@shareefj

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@shareefj

I'm struggling with indentation again and feel like I've been here before but haven't managed to find anything that works. All the examples and similar issues all point at using verilog-typedef-regexp but I haven't managed to get it to work yet. I do recall that on previous issues where this didn't work, I realised I had to set it in the child module for AUTO's to work, but in this case I've tried pretty much every permutation and it still fails.

As an example, how do I get my_special_t to be indented correctly?

package test_pkg;
  typedef enum logic
    {
     StateOne = 1'b0,
     StateTwo = 1'b1
     } my_special_t;
endpackage

module test
  import test_pkg::*;
  #(
    parameter int TestParam = 1
    )(
      input logic clk,
      input logic rst_n,
      input       my_special_t special
      );
endmodule

// Local Variables:
// verilog-library-directories:(".")
// verilog-typedef-regexp:"_t$"
// End:

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