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Feature Request: Autoformat/indent Verilog 2001 Module Headers #260

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veripoolbot opened this issue Jun 4, 2010 · 2 comments
Closed

Feature Request: Autoformat/indent Verilog 2001 Module Headers #260

veripoolbot opened this issue Jun 4, 2010 · 2 comments
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@veripoolbot
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@veripoolbot veripoolbot commented Jun 4, 2010


Author Name: Joachim Lechner
Original Redmine Issue: 260 from https://www.veripool.org
Original Date: 2010-06-04
Original Assignee: Michael McNamara


It would be nice to have the autoformat/indent feature also for verilog 2001 module headers.

e.g.:

module test_module(
  input wire [1:0]      pin1,
  input wire      pin2,
  input wire [1:0]      pin3,
  input wire        pin4,
  output wire     pin5,
  output wire [10:0] pin6,
  output reg     pin7,
  output reg  [1:0]     pin8
  );

to something like:

module test_module(
  input  wire [1:0]  pin1,
  input  wire        pin2,
  input  wire [1:0]  pin3,
  input  wire        pin4,
  output wire        pin5,
  output wire [10:0] pin6,
  output reg         pin7,
  output reg  [1:0]  pin8
  );

Best regards, Joachim

@veripoolbot
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@veripoolbot veripoolbot commented Jun 4, 2010


Original Redmine Comment
Author Name: Joachim Lechner
Original Date: 2010-06-04T07:32:07Z


Sorry now the example should be readable - see attached file.

@veripoolbot
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@veripoolbot veripoolbot commented Feb 21, 2011


Original Redmine Comment
Author Name: Michael McNamara
Original Date: 2011-02-21T06:46:28Z


Fixed with version 666 (oooh!) declarations are lined up inside modern style port declaration blocks.

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