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AUTOINST and SystemVerilog interfaces #270

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veripoolbot opened this issue Jul 19, 2010 · 5 comments
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AUTOINST and SystemVerilog interfaces #270

veripoolbot opened this issue Jul 19, 2010 · 5 comments
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@veripoolbot veripoolbot commented Jul 19, 2010


Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 270 from https://www.veripool.org
Original Date: 2010-07-19
Original Assignee: Wilson Snyder (@wsnyder)


See http://www.veripool.org/boards/15/topics/show/315-Verilog-mode-AUTOINST-and-SystemVerilog-interfaces

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@veripoolbot veripoolbot commented Jul 19, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-07-19T15:20:51Z


This is new behavior. The first part is to search for interfaces, this is easy.

What would you expect the output to be with the multiple modports?

Without any work, VM gives:

    autoinst_iface315_sub inst_if (/*AUTOINST*/
                                   // Outputs                                                            
                                   .b                    (b),
                                   .a                    (a),
                                   // Inputs                                                             
                                   .a                    (a),
                                   .b                    (b));

Which isn't too useful.

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@veripoolbot veripoolbot commented Jul 19, 2010


Original Redmine Comment
Author Name: Luis Gutierrez
Original Date: 2010-07-19T15:44:32Z


From the point of view of AUTOINST, I would expect verilog-mode to pay attention to the singal declarations (ie, input, output, logic, inout etc) and not the modports.

AUOTWIRE and AUTOREG would get a bit more messy depending on what modport is used but perhaps this can be implemented at a later stage.

May I suggest having a syntax/grammar for specifying the port in the AUTO_TEMPLATE that is very similar to SV, to ease the learning curve on the user?.

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@veripoolbot veripoolbot commented Jul 19, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-07-19T15:47:18Z


Ignoring the modports is easy enough. Can you give an example of what you mean by:

"May I suggest having a syntax/grammar for specifying the port in the AUTO_TEMPLATE that is very similar to SV, to ease the learning curve on the user?."

Unless it's directly related, can you put that in a separate bug? Thanks.

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@veripoolbot veripoolbot commented Jul 19, 2010


Original Redmine Comment
Author Name: Luis Gutierrez
Original Date: 2010-07-19T15:54:07Z


Thinking about it, it is unrelated.

thanks for looking into this.

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@veripoolbot veripoolbot commented Aug 18, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-08-18T14:19:07Z


Fixed in rev634.

Here's an example output; there may well be other issues as this is a fairly major change, let me know how it goes.

module top;
    autoinst_iface270_sub inst_if
      (/*AUTOINST*/
       // Interfaced
       .a                    (a),
       .b                    (b));

    ifio sub
      (/*AUTOINST*/
       // Interfaces
       .inst_if                   (inst_if));

endmodule

interface autoinst_iface270_sub;
    logic a;
    logic b;
    modport master_mp(input a, output b);
    modport slave_mp(output a, input b);
    modport monitor (input a, input b);
endinterface

module ifio
  (autoinst_iface270_sub inst_if);
endmodule

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