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alignment of assignment operators and comparison operators #399

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veripoolbot opened this issue Oct 14, 2011 · 2 comments
Closed

alignment of assignment operators and comparison operators #399

veripoolbot opened this issue Oct 14, 2011 · 2 comments
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@veripoolbot
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@veripoolbot veripoolbot commented Oct 14, 2011


Author Name: Max Bjurling
Original Redmine Issue: 399 from https://www.veripool.org
Original Date: 2011-10-14
Original Assignee: Michael McNamara


This code snippet does not align properly. The assignment operator <= is aligned to the comparison operator ==.
Verilog mode gives:

always @(*) begin
    if (sample_signal_with_long_name == 1'b1) begin
       data                          <= data_in;      
    end
end

but it should be

always @(*) begin
    if (sample_signal_with_long_name == 1'b1) begin
       data <= data_in;      
    end
end

@veripoolbot
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@veripoolbot veripoolbot commented Dec 15, 2011


Original Redmine Comment
Author Name: Michael McNamara
Original Date: 2011-12-15T18:46:12Z


Fixed in release 736 (released 12/10/11)

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@veripoolbot veripoolbot commented Feb 6, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-02-06T23:18:29Z


Resolved a while ago.

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