Join GitHub today
GitHub is home to over 40 million developers working together to host and review code, manage projects, and build software together.Sign up
Question: Issue with hooking up ports using conditional operators #564
Author Name: Gauravg Gupte
Iâ€™m using AUTO_TEMPLATE to conditionally connect outputs to different names depending on the instance number using the following syntax for a "if" statement.
All I want to do is hook up GcuReqArbGntVec0NnnW to even instances and GcuReqArbGntVec1NnnW to odd instances.(and use the expressions above to connect correct bits of the vector). However I get and end of file parsing error when I run AUTOS. However; if I try and do these expressions individually both of them work:
.GcuSSArb(.*)VecNnnW (GcuReqArbGntVec0NnnW[@"(/ @ 2)"]), // THIS WORKS WITH AUTOS
But when I try to put these 2 together it doesnt go through. Anything I am doing wrong? Is there any workaround to this?
Original Redmine Comment
Looks reasonable to me. Check you are using the most recent verilog-mode version, and if so paste a complete small example showing the problem and I'll take a look.