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Question: help on AUTOARG #756

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veripoolbot opened this issue May 31, 2014 · 3 comments
Closed

Question: help on AUTOARG #756

veripoolbot opened this issue May 31, 2014 · 3 comments
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@veripoolbot
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@veripoolbot veripoolbot commented May 31, 2014


Author Name: Jie Xiao
Original Redmine Message: 1354 from https://www.veripool.org


Hi, I am doing intergration work with others that don't use verilog-mode, they complain to me that AUTOARG input and output port list is hard to use because several ports in one line, they perfer one line for each port as following:

 module xxxx (/*AUTOARG*/
  //Outputs
  aport_o,
  bport_o,
  cport_o,
  //Inputs
  clk_i,
  rst_i,
  dport_i, 
   ...
 );

could you add one option for this. Thanks for your help
Arhtas Jie Xiao

I have updated verilog-mode.el
(defun verilog-auto-arg-ports ...
....
(insert (verilog-sig-name (car sigs)) ","
(insert "\n") //my update for switch line
and it works as what I expect except one indent issue

i have fixed indent issue by
(setq sigs (cdr sigs)
space "")))) // from space " "

@veripoolbot
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@veripoolbot veripoolbot commented May 31, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-31T11:52:55Z


Argument lists don't make sense since Verilog-2001. I'm curious why you aren't using a more modern format?

module xxxx (
//Outputs
output aport_o,
output bport_o,
output cport_o,
//Inputs
input clk_i,
input rst_i,
input dport_i,
...
);

@veripoolbot
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@veripoolbot veripoolbot commented May 31, 2014


Original Redmine Comment
Author Name: Jie Xiao
Original Date: 2014-05-31T13:09:25Z


I have tried v2k1, it is also fine to me, but as I said before, some people don't use verilog-mode, and they want get port list in such format.

thanks for your reply.

@veripoolbot
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@veripoolbot veripoolbot commented May 31, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-31T14:23:43Z


Ok, added verilog-auto-arg-format in verilog-mode-2014-05-31-3cd8144-vpo

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