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Question: AUTOINPUTEVERY #826

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veripoolbot opened this issue Oct 1, 2014 · 1 comment
Closed

Question: AUTOINPUTEVERY #826

veripoolbot opened this issue Oct 1, 2014 · 1 comment
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@veripoolbot veripoolbot commented Oct 1, 2014


Author Name: Vinod B
Original Redmine Message: 1439 from https://www.veripool.org


Is it possible to have an AUTOINPUTEVERY option just like AUTOOUTPUTEVERY such that every signal on the right hand side of a wire assignment is automatically made an input port?

@veripoolbot veripoolbot closed this Oct 1, 2014
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@veripoolbot veripoolbot commented Oct 1, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-10-01T19:10:13Z


Not easily, as at present verilog-mode does not parse any right hand sides of the assignments.

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