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support SV instances in port list with AUTOs #95

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veripoolbot opened this issue Apr 5, 2009 · 5 comments
Closed

support SV instances in port list with AUTOs #95

veripoolbot opened this issue Apr 5, 2009 · 5 comments
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@veripoolbot veripoolbot commented Apr 5, 2009


Author Name: David Rogoff
Original Redmine Issue: 75 from https://www.veripool.org
Original Date: 2009-04-05
Original Assignee: Wilson Snyder (@wsnyder)


AUTOs (e.g. AUTOINST, AUTOWIRE) don't work correctly with submodules that contain interface type ports.

Here's a simple case that works:

module submod
     (input wire clk,input wire reset,input wire start, output reg [7:0] count);
endmodule // submod

module top;
    /*AUTOWIRE*/
    submod submod0 (/*AUTOINST*/);
endmodule // top

Now, I add an interface to the ports of submod

interface my_svi;
    logic enable;
    logic error;
    logic [7:0] count2;
    modport master (
                    input enable,
                    output error,
                    output count2);
endinterface // my_svi

module submod
     (my_svi.master my_svi_port,
      input wire clk, input wire reset, input wire start, output reg [7:0] count );
endmodule // submod

module top;
    /*AUTOWIRE*/
    submod submod0 (/*AUTOINST*/);
endmodule // top

When I expand autos, I get this:

interface my_svi;
    logic enable;
    logic error;
    logic [7:0] count2;
    modport master (
                    input enable,
                    output error,
                    output count2);
endinterface // my_svi

module submod
     (my_svi.master my_svi_port,
      input wire clk, input wire reset, input wire start, output reg [7:0] count );
endmodule // submod

module top;
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire [7:0]           count;                  // From submod0 of submod.v
    // End of automatics
    submod submod0 (/*AUTOINST*/
                    // Outputs
                    .count               (count[7:0]),
                    // Inputs
                    .clk                 (clk),
                    .reset               (reset),
                    .start               (start));
endmodule // top

This ignores the interface port. I've run this in more complicated in where auto did really weird stuff, making up wires of random widths! I don't have an example of that here. Anyway, AUTOINST needs to understand and expand interface ports. Also, it would make sense to have an AUTOINTERFACE to go with AUTOWIRE and AUTOREG.

What it should look like is this:

module top;
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire [7:0]           count;                  // From submod0 of submod.v

    /*AUTOINTERFACE*/
    my_svi my_svi_port;  // sdfasdfasdf
        
    // End of automatics
    submod submod0 (/*AUTOINST*/
                    // Interfaces
                    .my_svi_port         (my_svi_port),
                    // Outputs
                    .count               (count[7:0]),
                    // Inputs
                    .clk                 (clk),
                    .reset               (reset),
                    .start               (start));
endmodule // top

Also, do AUTOs understand ports of type logic? Does AUTOWIRE? Should there be an AUTOLOGIC? Isn't SystemVerilog a massive pain with the increased features and complexity? :^)

Thanks,

David

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@veripoolbot veripoolbot commented Apr 5, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-04-05T11:05:49Z


Thanks for the good report. There's a lot of work here so it will be at least a few weeks.

BTW, you're right SystemVerilog is a pain to support. The big two problems are the "kitchen-sink" philosophy - there's many places where they could have made things more general and simplified, and worse that the language isn't a LR grammar and to parse requires a symbol table (ala C). That makes it very difficult to write "hackware" parsers. (If I was a paranoid person, I'd say much of the point of SystemVerilog complexity is to insure only the big CAD companies could implement it :)

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@veripoolbot veripoolbot commented Apr 24, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-04-24T20:39:51Z


BTW, I did think it would be cool to do this for those that name signals
the "right" way and want to have modports that do I/O into that interface:

interface x;
    logic x_y_a;
    logic x_y_b;
    logic y_x_c;
    modport in (
         /*AUTOMODPORT("input","x_y_.*")*/
         input x_y_a;
         input x_y_b;
         /*AUTOMODPORT("output","y_x_.*")*/
         output y_x_c;
    );
    modport in (
         /*AUTOMODPORT("output","x_y_.*")*/
         output y_x_c;
         /*AUTOMODPORT("input","y_x_.*")*/
         input x_y_a;
         input x_y_b;
    );
endinterface


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@veripoolbot veripoolbot commented May 4, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-04T20:00:31Z


The parsing was getting so nasty I'm making it much less general. The interface, modport and name need to be together without any `defines or comments, ie "intf.modport name" not "intf /hello/ . modport /attr/ name".

AUTOARG n/a - use v2k syntax
AUTOINOUTCOMP fixed
AUTOINOUTMODULE fixed
AUTOINOUT making hierarchy inouts
AUTOINST fixed
AUTOWIRE needs work

I want to make AUTOWIRE or a new one make the interface interconnection, but that requires a new parser step to look for interfaces the user has already declared, so I'll leave that for a later checkin.

Appropriately, this all happened to commit as Version 500!

Let me know how it looks.

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@veripoolbot veripoolbot commented May 4, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-04T22:07:28Z


David sends:

can you add the modport, if it is specified in the port list of the
submodule?

e.g.

module  myram
      (
         input wire          clk,
         input wire          reset,
         ram_if.slave        ram_if
         );

module top;
    myram myram0(
     /*AUTOINST*/
       // Interfaces
       .ram_if        (ram_if.slave),

       // Inputs
       .clk           (clk),
       .reset         (reset));

Another, although not a biggie since your AUTO is doing the typing:
Use, if specified (SVD variable??) .name port connections for any port
connected to a signal with the same name, which would be anything in
AUTOINST not using a template:

module top;
    myram myram0(
     /*AUTOINST*/
       // Interfaces
       .ram_if        (ram_if.slave),

       // Inputs
       .clk,
       .reset);

This is nice because it makes it obvious which ports connect to signals
that have a different name. Of course you can just use .*, but I've
threatened to shoot anyone in my group who uses that since it makes code
totally unreadable.

One more, while I'm here:
It would be great if you could carry over any comments from port
definitions to the instantiation:

module  myram
      (
         input wire      clk,  // main system clock
         input wire      reset, // synchronous reset
         ram_if.slave    ram_if   // RAM control interface
         );

module top;
    myram myram0(
     /*AUTOINST*/
       // Interfaces
       .ram_if        (ram_if.slave), // RAM control interface

       // Inputs
       .clk           (clk),  // main system clock
       .reset         (reset)); // synchronous reset

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@veripoolbot veripoolbot commented May 5, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-05T00:18:10Z


can you add the modport, if it is specified in the port list of the submodule?

Easy, done. Revision 501 on veripool.org

.name port connections

I don't want to do this (yet) because it would break Verilog 2001 files, and there's no reliable way to tell which language is in use. Also, it would mess up AUTOWIRE.

Comments from submodules

Sorry, I also don't want to do that, because it leads to a lot more changes when a lower level module changes, and more critically some comments are meta comments for tools, and propagating them can result in errors.

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