Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

AUTOWIRE misdeclares multidimensional arrays #986

Closed
veripoolbot opened this issue Oct 28, 2015 · 2 comments
Closed

AUTOWIRE misdeclares multidimensional arrays #986

veripoolbot opened this issue Oct 28, 2015 · 2 comments
Assignees
Labels

Comments

@veripoolbot
Copy link
Collaborator

@veripoolbot veripoolbot commented Oct 28, 2015


Author Name: Brad Dobbie
Original Redmine Issue: 986 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


module auto_mda;

    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire [0] [1:0]	mda;			// From a0 of a.v, ...
    wire [1:0]		sda;			// From a0 of a.v, ...
    // End of automatics

    /* a AUTO_TEMPLATE (
     .sda				(sda[@]),
     .mda				(mda[@][]),
     ); */
    a a0
      (/*AUTOINST*/
       // Outputs
       .sda				(sda[0]),		 // Templated
       .mda				(mda[0][1:0]));		 // Templated
    a a1
      (/*AUTOINST*/
       // Outputs
       .sda				(sda[1]),		 // Templated
       .mda				(mda[1][1:0]));		 // Templated

    b b
      (/*AUTOINST*/
       // Inputs
       .sda				(sda[1:0]),
       .mda				(mda/*[1:0][1:0]*/));

endmodule

module a (output 	sda,
	  output [1:0] 	mda)
endmodule

module b (input [1:0]	   sda,
	  input [1:0][1:0] mda);
endmodule

For some reason Verilog-mode correctly declares "sda", but generates invalid syntax for "mda". In the past, I've worked around by hand declaring the signals. But it seems like verilog-mode should be able to figure out the correct declaration (which it does correctly for typedef'ed signals).

@veripoolbot
Copy link
Collaborator Author

@veripoolbot veripoolbot commented Oct 31, 2015


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-10-31T00:44:54Z


Brad, the first problem is the syntax is ambiguous, should it make a packed or unpacked array? The second and probably bigger problem is the packing function to combine vectors is already fairly complicated, so this won't be something quick to improve.

@veripoolbot
Copy link
Collaborator Author

@veripoolbot veripoolbot commented Dec 21, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-21T15:12:10Z


Agree would be useful, but closing due to age as unlikely to get fixed in the medium term.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Linked pull requests

Successfully merging a pull request may close this issue.

None yet
2 participants
You can’t perform that action at this time.