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AUTOWIRE misdeclares multidimensional arrays #986
Author Name: Brad Dobbie
Original Assignee: Wilson Snyder (@wsnyder)
For some reason Verilog-mode correctly declares "sda", but generates invalid syntax for "mda". In the past, I've worked around by hand declaring the signals. But it seems like verilog-mode should be able to figure out the correct declaration (which it does correctly for typedef'ed signals).
Original Redmine Comment
Brad, the first problem is the syntax is ambiguous, should it make a packed or unpacked array? The second and probably bigger problem is the packing function to combine vectors is already fairly complicated, so this won't be something quick to improve.