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System Verilog 'import <package file>::*' results in syntax error #1089
Author Name: Ed Carstens
Original Assignee: Wilson Snyder (@wsnyder)
I have the following line in a System Verilog interconnect module:
that is resulting in the following error:
%Error: :59: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING
I have found that inserting a line to include the package file before the import works:
I don't think this include should be required if the package files can be read and parsed prior to the import, as you would do for a simulation.
Original Redmine Comment
The SystemVerilog specification requires that you declare packages before using them. Therefore you must either `include or put the package file on the command line.