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How to pass SV packages to verilog::getopt? #1132

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veripoolbot opened this issue Mar 6, 2017 · 4 comments
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How to pass SV packages to verilog::getopt? #1132

veripoolbot opened this issue Mar 6, 2017 · 4 comments
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@veripoolbot veripoolbot commented Mar 6, 2017


Author Name: Shareef Jalloq
Original Redmine Issue: 1132 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Hi there,

I've just switched to using SV and am struggling to modify my scripts based on Verilog::Netlist. I can't work out how to pass in the packages that should be compiled in order to resolve the 'import package::*;' references.

We have all our packages that should be compiled in a single pkg_filelist. I've tried passing this to verilog::getopt in a number of ways but the packages are always removed from ARGV and are ignored as a parameter.

I've added a testcase of what I'm trying to do. Run 'make test' from the testcase/ directory and it should be printing out the list of packages and the top level module.

What am I doing wrong? I'm expecting either the Verilog::Getopt to parse the params correctly or pass on anything to ARGV to that I can iterate over the files and load them using Verilog::Netlist->read_file.

Short version of what's in the testcase:

my $opt = new Verilog::Getopt;
$opt->parameter( qw( +libext+.sv
-sv
-f ./packages/my_package_filelist # gets ignored and lost
./packages/my_extra_pkg.sv # gets ignored and lost
+incdir+./include
-y ./verilog
) );

@argv = $opt->parameter(@argv);

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@veripoolbot veripoolbot commented Mar 6, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-03-06T12:21:35Z


The second call to parameter erases the previous arguments. I don't recall why it was written this way and is certainly confusing, but at this stage to avoid breaking programs I updated the documentation.

@ARGV = $opt->parameter( qw( +libext+.sv
                      -sv
                      -f ./packages/my_package_filelist
                      ./packages/my_extra_pkg.sv
                      +incdir+./include
                      -y ./verilog
                  ), @ARGV);

@veripoolbot veripoolbot closed this Mar 6, 2017
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@veripoolbot veripoolbot commented Mar 6, 2017


Original Redmine Comment
Author Name: Shareef Jalloq
Original Date: 2017-03-06T12:25:28Z


I'm not sure that's the solution as my testcase shows most of the parameters are still presented when using $opt->get_parameters(). Only the package file is missing.

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@veripoolbot veripoolbot commented Mar 6, 2017


Original Redmine Comment
Author Name: Shareef Jalloq
Original Date: 2017-03-06T12:28:13Z


Hmmm, I updated my testcase with your solution and the packages are now output to ARGV, but so is the "-sv" switch. Is that a known bug?

$ make test
./run_verilog_getopt top_design.sv
ARGV:
-sv
package_1.sv
package_2.sv
./packages/my_extra_pkg.sv
top_design.sv

get_parameters:
+libext+.v+.sv
+incdir+.
+incdir+./include
-y
.
-y
./verilog


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@veripoolbot veripoolbot commented Mar 6, 2017


Original Redmine Comment
Author Name: Shareef Jalloq
Original Date: 2017-03-06T12:31:19Z


Sorry, looks like I was reading the 'vhier' doco and thought I needed that switch. It's not recognised by Verilog::Getopt.

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