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Verilog::SigParser problems with package ordering #1179

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veripoolbot opened this issue Jun 23, 2017 · 6 comments
Closed

Verilog::SigParser problems with package ordering #1179

veripoolbot opened this issue Jun 23, 2017 · 6 comments

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@veripoolbot veripoolbot commented Jun 23, 2017


Author Name: Shareef Jalloq
Original Redmine Issue: 1179 from https://www.veripool.org


Hi there,

I'm seeing an error reported when trying to parse a file that uses wildcard imports. It seems strange as vppreproc and Verilog::Netlist both parse these fine. I'm using version 3.422.

The error is:

%Error: /path/to/file.sv:84: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING

The script looks like:

     my $vp = Verilog::Preproc->new( options => $opt  );
     my $parser = MySigParser->new( options => $opt );

     foreach (@files) {
         print "$_\n";
         $vp->open( filename => $_ );
         $parser->parse_preproc_file($vp);
     }

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@veripoolbot veripoolbot commented Jun 23, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-06-23T14:20:20Z


The language standard requires packages be declared before they are referenced, so most likely that's resulting in this message. Include the packages before you use them.

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@veripoolbot veripoolbot commented Jun 23, 2017


Original Redmine Comment
Author Name: Shareef Jalloq
Original Date: 2017-06-23T14:26:26Z


So what's the best way to use SigParser? How do you build the file tree such that it parses in the correct order? I just assumed it would work like Verilog::Netlist if you passed in a VC file.

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@veripoolbot veripoolbot commented Jun 23, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-06-23T14:31:06Z


It does work like Netlist. You just need the file list in the proper order, with files containing packages first, or have your modules `include the package definitions, just as most simulators require.

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@veripoolbot veripoolbot commented Jun 23, 2017


Original Redmine Comment
Author Name: Shareef Jalloq
Original Date: 2017-06-23T14:41:24Z


Our VC file has all the packages declared at the head of the file.

So what you're saying is that if you want to use SigParser, you have to manually build the file tree or update the source to `include?

Edit: I tried to `include the package but then I get an 'unexpect package' error from SigParse.

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@veripoolbot veripoolbot commented Jun 23, 2017


Original Redmine Comment
Author Name: Shareef Jalloq
Original Date: 2017-06-23T14:59:59Z


Fixed it.

I remembered that when parsing the options file using Verilog::Getopt->parameter, it returns a list of files. This is how we get the packages in our other scripts.

Thanks.

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@veripoolbot veripoolbot commented Jun 23, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-06-23T15:08:20Z


Great!

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