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Multi dimensional arrays #1206

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veripoolbot opened this issue Sep 11, 2017 · 1 comment
Closed

Multi dimensional arrays #1206

veripoolbot opened this issue Sep 11, 2017 · 1 comment

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@veripoolbot
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@veripoolbot veripoolbot commented Sep 11, 2017


Author Name: Leon Medpum
Original Redmine Issue: 1206 from https://www.veripool.org


is this expected to work?

module submod1 (
     input [2:0] net1
);
endmodule

module top ();
     wire [1:0] [2:0] neta;

     submod1 submod1
     (.net1 (neta[1])
     );
endmodule

It doesn't seem to be documented in IEEE.1364-2005, but it is valid systemverilog (IEEE Std 1800™-2012 section 7.4.5)

here is a test program:

#!/usr/bin/env perl

use strict;
use warnings;

use Verilog::Netlist;
use Data::Dumper;

my $file = shift @ARGV;
1. prepare netlist
my $Opt = new Verilog::Getopt(filename_expansion=>1);
$Opt->libext(".sv");

my $nl = new Verilog::Netlist(
                  options => $Opt,
                  synthesis => 0,
                  use_pinselects => 1,
                  # link_read_nonfatal => 1
                  );
$nl->read_file(filename => $file);

1. read in any sub modules
$nl->link();
$nl->lint();
$nl->exit_if_error();

my $mod = $nl->find_module('top');
my @nets = $mod->nets();
print "Module: " . $mod->name() . "\n";
foreach my $net (@nets) {
     print "    Net: " . $net->name() . " MSB: " . $net->msb() . " LSB: " . $net->lsb() . "\n";
}

And the output:

Module: top
     Net: neta MSB: 1:0][2 LSB: 0

The net->msb() returned is not an integer as expected. I am not sure if this syntax is supposed to be supported or not.

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@veripoolbot veripoolbot commented Sep 13, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-09-13T00:12:48Z


This is a side effect of 2001 parsing that it's better not to clean up. The documentation for ports already indicated this was for Verilog 1995 only. I did however commit making the docs a bit clearer and a test for this.

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