Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 129 from https://www.veripool.org
Original Date: 2007-01-24
Original Assignee: Wilson Snyder (@wsnyder)
This bug was cloned from Perl-RT, rt24552.
Email addresses have have been truncated.
Id: 24552
Status: resolved
Left: 0 min
Queue: Verilog-Perl
Owner: Nobody
Requestors: takeo.komiyama@
Severity: (no value)
Wed Jan 24 23:41:24 2007 takeo.komiyama@ - Ticket created
Subject: wire declaration is wrong when add new net
Date: Thu, 25 Jan 2007 13:40:53 +0900
To: bug-Verilog-Perl@
From: Takeo Komiyama <takeo.komiyama@>
Hi,
I found the strange behavior in Verilog-Perl 2.370 release.
When I add new wire using with new_net() function.
verilog_text() generate wrong verilog sytax code (missing wire declaration).
----- Test code ------------------------------
#! /usr/bin/env perl
use strict;
use Verilog::Netlist;
use Verilog::Netlist::Net;
my $nl = new Verilog::Netlist (keep_comments=>1);
$nl->read_file (filename=>"test.v");
$nl-> link();
my $module = $nl -> find_module ("test");
my $newNet = $module -> new_net (name=>"new_wire");
print $module -> verilog_text();
----- Test code ------------------------------
----- Test data ------------------------------
module top;
wire a;
wire b;
test inst1
(.a(a),
.b(b)
);
endmodule
module test (
input a,
output b
);
endmodule
----- Test data ------------------------------
Above sample generate,
user@hoge[130]% ./test.pl
module test (
a, b);
input a;
output b;
new_wire; <---- Here. No wire declaration.
endmodule
So, I modified Verilog::Netlist::Net as,
--------- Patch -------------------------------------------
*** Net.pm~ 2007-01-22 21:28:00.000000000 +0900
--- Net.pm 2007-01-22 21:28:18.000000000 +0900
***************
*** 110,115 ****
--- 110,119 ----
$type = "output" if $self->port->direction eq "out";
$type = "inout" if $self->port->direction eq "inout";
}
+ else
+ {
+ $type = "wire";
+ }
$type .= " signed" if $self->signed;
return $type;
}
--------- Patch -------------------------------------------
Then I confirm this problem is fixed.
module test (
a, b);
input a;
output b;
wire new_wire;
endmodule
P.S. At first I tried to create bitcard account, but I can not enter
event I
create account. So I directory sent this message.
Thu Jan 25 15:27:35 2007 WSNYDER - Correspondence added
When you call new_net, pass in a type of wire like this:
new_net(name=>'....', type=>'wire')
and it will be correctly created. I'll make the type=>wire addition
be the default in the next release.
Thu Jan 25 15:27:44 2007 RT_System - Status changed from 'new' to 'open'
Thu Jan 25 15:27:47 2007 WSNYDER - Status changed from 'open' to 'resolved'
The text was updated successfully, but these errors were encountered:
Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 129 from https://www.veripool.org
Original Date: 2007-01-24
Original Assignee: Wilson Snyder (@wsnyder)
This bug was cloned from Perl-RT, rt24552.
Email addresses have have been truncated.
Wed Jan 24 23:41:24 2007 takeo.komiyama@ - Ticket created
Thu Jan 25 15:27:35 2007 WSNYDER - Correspondence added
Thu Jan 25 15:27:44 2007 RT_System - Status changed from 'new' to 'open'
Thu Jan 25 15:27:47 2007 WSNYDER - Status changed from 'open' to 'resolved'
The text was updated successfully, but these errors were encountered: