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vhier: support for SystemVerilog interfaces? #13
This may be an enhancment vs. a bug.
I'm using vhier to find all the files used in my design + testbench. It doesn't like the SV interfaces I'm using. Specifically, the following items within an interface cause errors:
Here's a sample file to illustrate the problem. The error messages I get are embedded as comments in the file. I used ifdefs to exclude the unsupported code and proceed to the next error.
Original Redmine Comment
The Verilog::Parser (what vhier uses) doesn't yet understand SystemVerilog interfaces.