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vhier: support for SystemVerilog interfaces? #13

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veripoolbot opened this issue Jun 4, 2008 · 3 comments
Closed

vhier: support for SystemVerilog interfaces? #13

veripoolbot opened this issue Jun 4, 2008 · 3 comments
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@veripoolbot veripoolbot commented Jun 4, 2008


Author Name: John Dickol
Original Redmine Issue: 13 from https://www.veripool.org
Original Date: 2008-06-04
Original Assignee: Wilson Snyder (@wsnyder)


This may be an enhancment vs. a bug.

I'm using vhier to find all the files used in my design + testbench. It doesn't like the SV interfaces I'm using. Specifically, the following items within an interface cause errors:

  • port list
  • signal (wire, etc.) definitions
  • clocking blocks
  • always blocks

Here's a sample file to illustrate the problem. The error messages I get are embedded as comments in the file. I used ifdefs to exclude the unsupported code and proceed to the next error.

vhier_ifc.sv:

interface ifc(

// %Error: vhier_ifc.sv:6: Signal declaration outside of module definition
// Can't call method "_portsordered" on an undefined value at /usr/local/share/perl5/site_perl/5.8.5/i686-linux/Verilog/Netlist/File.pm line 113.
`ifndef NO_PORTS
         input bit clk
`endif
);

  wire [31:0] addr;
  wire [31:0] data;
  int count = 0;

// %Error: vhier_ifc.sv:16: syntax error, unexpected "clocking"
`ifndef NO_CLOCKING
  clocking mck @(posedge clk);
     default input #1 output #1;
     output addr, data;
  endclocking

  clocking pck @(posedge clk);
     default input #1 output #1;
     input addr, data;
  endclocking
`endif

// %Error: vhier_ifc.sv:29: syntax error, unexpected "always"
`ifndef NO_ALWAYS
  always @(posedge clk) count = count+1;
`endif

  modport master  (clocking mck);
  modport passive (clocking pck);

endinterface

module top;
  bit clk = 0;

// %Error: vhier_ifc.sv:41: Cannot find ifc
  ifc ifc_1(clk);
endmodule

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@veripoolbot veripoolbot commented Jun 4, 2008


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-06-04T16:55:46Z


The Verilog::Parser (what vhier uses) doesn't yet understand SystemVerilog interfaces.
This will be done at some point, but not soon. If you'd like to help out getting this working, let me know.

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@veripoolbot veripoolbot commented Apr 7, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-04-07T10:34:43Z


This is fixed in the beta candidate in GIT. It will be in 3.200.

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@veripoolbot veripoolbot commented Apr 15, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-04-15T15:35:46Z


In 3.200.

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