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Verilog::EditFiles misses module declarations where module keyword and module name are on separate lines #1311
Original Assignee: Wilson Snyder (@wsnyder)
I stumbled onto Verilog::EditFiles recently when looking for a tool that could split up a file and create one file per module. It's very neat!
However, I discovered an issue. I've been using it to post-process the output from a synthesis compiler, which-- for sufficiently long module names-- produces output with the name of the module on a separate line from the "module" keyword, like this:
The EditFiles command misses this. It does not identify this as a module declaration and will then fail when it sees the next "endmodule", because it thinks it missed a declaration.
Our simulator (Cadence Incisive-- ius) thinks this is valid Verilog code, however, and the file containing module declarations of this form is properly interpreted.
I wrote some hacky Perl code to pre-process the file and clean up module declarations like this, which works. But it'd be nice if the EditFiles command could be fixed to handle this case correctly.
Original Redmine Comment
Thanks for reporting this.
Attached is a patch to fix this. I think I won't be applying this, as I know some people simply copy and modify this code for themselves, and I'm reluctant to make the code more complicated. If some others see the same problem, I'll reconsider.