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Vhier : Usage to display whole hierarchy of a pin or a port in a module or sub-module. #1463
Author Name: Utkarsh Khanna
Original Assignee: Utkarsh Khanna
Suppose I have a verilog file with modules and lots of sub modules and also with pins inside the submodule.
Original Redmine Comment
This is not supported by vhier, and is unlikely to be added in the future, sorry. To do this you'd need to write your own perl program that uses the Verilog::Netlist package.