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Vhier : Usage to display whole hierarchy of a pin or a port in a module or sub-module. #1463

veripoolbot opened this issue Jun 13, 2019 · 1 comment


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@veripoolbot veripoolbot commented Jun 13, 2019

Author Name: Utkarsh Khanna
Original Redmine Issue: 1463 from

Original Assignee: Utkarsh Khanna

Suppose I have a verilog file with modules and lots of sub modules and also with pins inside the submodule.
I want to display the whole address of the pin or port input by user


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@veripoolbot veripoolbot commented Jun 14, 2019

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-06-14T01:14:39Z

This is not supported by vhier, and is unlikely to be added in the future, sorry. To do this you'd need to write your own perl program that uses the Verilog::Netlist package.

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