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macro with systemVerilog lexical delimiter fails if white spaces present in macro calling #158
This bug was cloned from Perl-RT, rt34429.
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Tue Mar 25 17:31:13 2008 admin@ - Ticket created
Thu Mar 27 10:38:41 2008 WSNYDER - Correspondence added
Thu Mar 27 10:38:45 2008 RT_System - Status changed from 'new' to 'open'
Thu Mar 27 10:38:46 2008 WSNYDER - Status changed from 'open' to 'resolved'