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macro with systemVerilog lexical delimiter fails if white spaces present in macro calling #158

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veripoolbot opened this issue Mar 25, 2008 · 0 comments
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@veripoolbot veripoolbot commented Mar 25, 2008


Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 158 from https://www.veripool.org
Original Date: 2008-03-25
Original Assignee: Wilson Snyder (@wsnyder)


This bug was cloned from Perl-RT, rt34429.

Email addresses have have been truncated.

Id: 	34429
Status: 	resolved
Left: 	0 min
Queue: 	Verilog-Perl
Owner: 	Nobody
Requestors: 	admin@

Severity: 	(no value)

Tue Mar 25 17:31:13 2008 admin@ - Ticket created

Subject: 	macro with systemVerilog lexical delimiter fails if white spaces present in macro calling
Date: 	Tue, 25 Mar 2008 14:30:41 -0700 (PDT)
To: 	bug-Verilog-Perl@
From: 	Vladimir Matveyenko <admin@>

Verilog-Perl-3.012
perl, v5.8.8 built for cygwin-thread-multi-64int
CYGWIN_NT-5.1 ecwm0clloan2 1.5.25(0.156/4/2) 2008-03-05 19:27 i686 Cygwin
I'm reporting an issue with macro expansion.
It appears that preprocessor capturing white spaces from the macro calling parameters and using them in actual macro text. This causes problems if SystemVerilog `` lexical delimiter is used in the macro.

Here is an example of harmless expansion:
// macro defined
`define add(a,b) (a+b)
// macro called like this:
`add(x, y) // expansion produces (x+ y)

// Here is macro defined with SystemVerilog delimiter

// --- start of source verilog ---
`define ADD_UP(a,c) \
wire tmp_``a = a; \
wire tmp_``c = tmp_``a + 1; \
assign c = tmp_``c ;
module test1 ( input wire d1, output wire o1, o2 );
`ADD_UP(d1,o1) // expansion is OK
`ADD_UP(d1, o2) // expansion is bad
endmodule
// --- end of source verilog ---

// --- start of post-processed verilog ---
`line 1 "junk1.v" 1

module test1 ( input wire d1, output wire o1, o2 );
wire tmp_d1 = d1; wire tmp_o1 = tmp_d1 + 1; assign o1 = tmp_o1 ; // PASS MACRO
wire tmp_d1 = d1; wire tmp_ o2 = tmp_d1 + 1; assign o2 = tmp_ o2 ; // FAIL MACRO
endmodule
// --- end of post-processed verilog ---

Steps to duplicate the problem:

1) vppp test1.v > test1.vppp
2) vhier test1.vppp
%Error: junk1.v:9: syntax error, unexpected IDENTIFIER, expecting ',' or ';'
%Error: junk1.v:9: syntax error, unexpected IDENTIFIER, expecting ',' or ';'

Thank you

Thu Mar 27 10:38:41 2008 WSNYDER - Correspondence added

Thanks for the good example. This is fixed in the next upcomming
release, perhaps Monday. The patch is large, let me know if you want
it earlier.

There were other spacing bugs and macro-in-macro bugs that I found
related to this too.

I'd also note that spaces AFTER the parameter do not seem to get
compressed in other simulators, IE

`call(a,b) === `call( a,b)
but `call(a,b) !== `call(a ,b)

Thu Mar 27 10:38:45 2008 RT_System - Status changed from 'new' to 'open'

Thu Mar 27 10:38:46 2008 WSNYDER - Status changed from 'open' to 'resolved'

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