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Bug in Verilog-Perl - MIN:TYP:MAX delays in assign #160

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veripoolbot opened this issue Mar 31, 2008 · 0 comments
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Bug in Verilog-Perl - MIN:TYP:MAX delays in assign #160

veripoolbot opened this issue Mar 31, 2008 · 0 comments
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@veripoolbot veripoolbot commented Mar 31, 2008


Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 160 from https://www.veripool.org
Original Date: 2008-03-31
Original Assignee: Wilson Snyder (@wsnyder)


This bug was cloned from Perl-RT, rt34575.

Email addresses have have been truncated.

Id: 	34575
Status: 	resolved
Left: 	0 min
Queue: 	Verilog-Perl
Owner: 	Nobody
Requestors: 	MSCHARRER <martin@>

Severity: 	(no value)

Mon Mar 31 11:32:15 2008 MSCHARRER - Ticket created

Subject: 	Bug in Verilog-Perl - MIN:TYP:MAX delays in assign
Date: 	Mon, 31 Mar 2008 16:31:36 +0100
To: 	bug-Verilog-Perl@
From: 	Martin Scharrer <martin@>

Hello,

I'm using the tool 'vhier' included in Verilog-Perl which uses
Verilog::Language to print the hierarchy of my Verilog files. My code is
mostly Verilog1995 with some minor exceptions in some test-bench files
where I use the 'generate' block.
The used versions are
Perl 5.8.8
vhier: # $Id: vhier 49328 2008-01-07 16:28:25Z wsnyder $
Verilog-Perl-3.023 from CPAN

The parser can't handle assignments which uses the MIN:TYP:MAX delay
syntax for falling and rising edges.
Please see the example below:

module test;
wire a,b,c,d;
assign #(0,0) a = 1; // Works
assign #(0:1:2) b = 1; // Works
assign #(0:1:2,0:1:2) c = 1; // Does not work
assign #(0:1:2,0) d = 1; // Does not work
endmodule

%Error: test.v:5: syntax error, unexpected ',', expecting ')'
Exiting due to errors

This is valid Verilog code in my opinion.

Thank you,
Martin Scharrer

Mon Mar 31 17:05:29 2008 WSNYDER - Correspondence added

Thanks for the case.

This will be fixed in the next release. The patch is below:

===================================================================
--- Parser/VParseBison.y (revision 52625)
+++ Parser/VParseBison.y (working copy)
@@ -747,10 +747,9 @@
;

delay: '#' dlyTerm { } /* ignored */
- | '#' '(' dlyInParen ')' { } /* ignored */
- | '#' '(' dlyInParen ',' dlyInParen ')' { } /*
ignored */
- | '#' '(' dlyInParen ',' dlyInParen ',' dlyInParen ')'
{ } /* ignored */
- | '#' '(' dlyInParen ':' dlyInParen ':' dlyInParen ')'
{ } /* ignored */
+ | '#' '(' minTypMax ')' { } /* ignored */
+ | '#' '(' minTypMax ',' minTypMax ')' { } /*
ignored */
+ | '#' '(' minTypMax ',' minTypMax ',' minTypMax ')'
{ } /* ignored */
;

dlyTerm: yaID { }
@@ -759,7 +758,9 @@
| yaTIMENUM { }
;

-dlyInParen: expr { }
+// IEEE: mintypmax_expression and constant_mintypmax_expression
+minTypMax: expr { }
+ | expr ':' expr ':' expr { }
;

sigAndAttr: sigId sigAttrListE { $<fl>$=$<fl>1;
$$=$1; }

Mon Mar 31 17:05:40 2008 RT_System - Status changed from 'new' to 'open'

Mon Mar 31 17:05:43 2008 WSNYDER - Status changed from 'open' to 'resolved'

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