Bug in Verilog-Perl - MIN:TYP:MAX delays in assign #160
This bug was cloned from Perl-RT, rt34575.
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Mon Mar 31 11:32:15 2008 MSCHARRER - Ticket created
Mon Mar 31 17:05:29 2008 WSNYDER - Correspondence added
Mon Mar 31 17:05:40 2008 RT_System - Status changed from 'new' to 'open'
Mon Mar 31 17:05:43 2008 WSNYDER - Status changed from 'open' to 'resolved'
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