Join GitHub today
GitHub is home to over 40 million developers working together to host and review code, manage projects, and build software together.Sign up
An example in Verilog::EditFiles doesn't work #222
Bug via RT
Thu Mar 11 01:45:25 2010: Request 55460 was acted upon.
An example in Verilog::EditFiles, SYNOPSIS section doesn't work.
Trying to run (under Cygwin):
produces the following error:
It works with this: