An example in Verilog::EditFiles doesn't work #222
Bug via RT
Thu Mar 11 01:45:25 2010: Request 55460 was acted upon.
An example in Verilog::EditFiles, SYNOPSIS section doesn't work.
Trying to run (under Cygwin):
produces the following error:
It works with this:
The text was updated successfully, but these errors were encountered: