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Add support for complex ports in Verilog-Perl #262

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veripoolbot opened this issue Jun 8, 2010 · 2 comments
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Add support for complex ports in Verilog-Perl #262

veripoolbot opened this issue Jun 8, 2010 · 2 comments
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@veripoolbot veripoolbot commented Jun 8, 2010


Author Name: Evgeni Stavinov
Original Redmine Issue: 262 from https://www.veripool.org
Original Date: 2010-06-08
Original Assignee: Wilson Snyder (@wsnyder)


The following port declaration causes an error: "unexpected '{'. expecting CLASS-IDENTIFIER..."

module my_module ( Y, {A1, A2} , B, psup, nsup );
output Y;
input A1, A2, B;
input psup, nsup;
...

This is according to the Verilog specification of complex module ports.

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@veripoolbot veripoolbot commented Jun 8, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-06-08T22:56:53Z


Thanks for the case.

Fixed in git for next release 3.241+

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@veripoolbot veripoolbot commented Jun 21, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-06-21T23:47:07Z


In 3.250.

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