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Print verilog comment #409

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veripoolbot opened this issue Oct 29, 2011 · 6 comments
Closed

Print verilog comment #409

veripoolbot opened this issue Oct 29, 2011 · 6 comments
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@veripoolbot veripoolbot commented Oct 29, 2011


Author Name: Salem Boudjelel
Original Redmine Issue: 409 from https://www.veripool.org
Original Date: 2011-10-29
Original Assignee: Wilson Snyder (@wsnyder)


I tried Verilog-Perl but I am faving an issue with Verilog comment
Perhaps I am not using Verilog::Netlist package correctly.
It seems that $sig->comment() doesn't work...

Regards,
Salem

Here the code:

use strict;
use warnings;
use Verilog::Netlist;

1. prepare netlist
my $nl = new Verilog::Netlist(keep_comments => 1,);
$nl->read_file(filename => './top.v');

1. read in any sub modules
$nl->link();
$nl->lint();
$nl->exit_if_error();

print "Module names in netlist:\n";
for my $mod ( $nl->modules() ) {
    print $mod->name(), "\n";
}
print "\n";

for my $mod ( $nl->top_modules_sorted() ) {
    show_hier($mod, '', '', '');
}

sub show_hier {
    # Recursively descend through module hierarchy,
    # printing each module name and full hierarchical
    # specifier, all module port names, and all
    # instance port connections.
    my $mod      = shift;
    my $indent   = shift;
    my $hier     = shift;
    my $cellname = shift;
    if ($cellname) {
        $hier .= ".$cellname";
    }
    else {
        $hier = $mod->name();
    }
    print "${indent}ModuleName=", $mod->name(), "  HierInstName=$hier\n";
    $indent .= '   ';

    for my $sig ($mod->ports_sorted()) {

        print $indent, 'PortDir=', sigdir($sig->direction()), ' PortName=', $sig->name(), "\n";
        print $indent,  ' Port comment=', $sig->comment(), "\n";
    }

    for my $cell ($mod->cells_sorted()) {
        for my $pin ($cell->pins_sorted()) {
            print $indent, ' PinName=', $pin->name(), ' NetName=', $pin->netname(), "\n";
        }

        show_hier($cell->submod(), $indent, $hier, $cell->name()) if $cell->submod();
    }
}

sub sigdir {
    # Change "in"  to "input"
    # Change "out" to "output"
    my $dir = shift;
    return ($dir eq 'inout') ? $dir : $dir . 'put';
}

Result:

Module names in netlist:
buff
inv
top

ModuleName=top  HierInstName=top
    ModuleName=buff  HierInstName=top.b0
       PortDir=input PortName=buf_in
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
        Port comment=
       PortDir=inout PortName=out
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
        Port comment=
        PinName=in NetName=buf_in
        PinName=out NetName=a
       ModuleName=inv  HierInstName=top.b0.i0
          PortDir=input PortName=in
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
           Port comment=
          PortDir=output PortName=out
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
           Port comment=
        PinName=in NetName=a
        PinName=out NetName=buf_out
       ModuleName=inv  HierInstName=top.b0.i1
          PortDir=input PortName=in
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
           Port comment=
          PortDir=output PortName=out
Use of uninitialized value in print at test.pl line 47, <DATA> line 98.
           Port comment=


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@veripoolbot veripoolbot commented Oct 31, 2011


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-10-31T17:16:49Z


Can you send an example of the code with comments?

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@veripoolbot veripoolbot commented Nov 1, 2011


Original Redmine Comment
Author Name: Salem Boudjelel
Original Date: 2011-11-01T22:12:36Z


I guess you mean verilog code...
Here after the code I used.

module top;
    buff b0 ();
endmodule

module buff (buf_in, buf_out);
    input buf_in;
    inout out;
    wire  a;
    inv i0 (.in(buf_in), .out(a      ));
    inv i1 (.in(a     ), .out(buf_out));
endmodule

module inv (in, out);
    input  in;
    output out;
    assign out = ~in;
endmodule

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@veripoolbot veripoolbot commented Nov 1, 2011


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-11-01T22:17:05Z


Um, that code has no comments, so asking for a net's comment will of course return undef. Am I missing something? What are you expecting?

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@veripoolbot veripoolbot commented Nov 1, 2011


Original Redmine Comment
Author Name: Salem Boudjelel
Original Date: 2011-11-01T22:18:40Z


Sorry forget the last message, here after the right code
I used this verilog code just for test purpose.

module top;
    buff b0 ();
endmodule

module buff (buf_in, buf_out);
    input buf_in; //My comment for buf_in
    inout out; //My comment for out
    wire  a;
    inv i0 (.in(buf_in), .out(a      ));
    inv i1 (.in(a     ), .out(buf_out));
endmodule

module inv (in, out);
    input  in; //My comment for in
    output out; //My comment for out
    assign out = ~in;
endmodule

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@veripoolbot veripoolbot commented Nov 1, 2011


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-11-01T22:32:07Z


The comments are attached to the net object, not the port.

for my $sig ($mod->nets_sorted()) {
    print $indent, ' NetName=', $sig->name(), "\n";
    print $indent,  '****************' if $sig->comment;
    print $indent,  ' Net comment=', $sig->comment()||"", "\n";
}
@veripoolbot veripoolbot closed this Nov 1, 2011
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@veripoolbot veripoolbot commented Nov 1, 2011


Original Redmine Comment
Author Name: Salem Boudjelel
Original Date: 2011-11-01T22:37:11Z


Well you need to correct the Verilog::Netlist::Port doc
$self->comment
Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

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